Method of micromachining a multi-part cavity

Details Method of micromachining a multi-part cavity Method of micromachining a multi-part cavity

2002-07-11

2004-12-07

Norton, Nadine G. (Department: 1765)

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating of groove or through hole

C216S002000, C216S018000, C216S046000, C438S700000, C438S710000, C438S733000

Reexamination Certificate

active

06827869

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of micromachining a multi-part cavity in a substrate, wherein different parts of the cavity may be formed to have different shapes. The present invention also pertains to a method of forming a multi-part cavity in a semiconductor substrate, for the purpose of manufacturing a semiconductor device.
2. Brief Description of the Background Art
Numerous methods for preparing semiconductor devices which include a trench in a silicon crystal silicon or polycrystalline silicon substrate have been described in the art. A few of these methods are described below.
U.S. Pat. Nos. 4,895,810 and 5,182,234, issued Jan. 23, 1990 and Jan. 26, 1993, respectively, to Meyer and Hollinger et al., disclose methods for creating a device structure where a trench is formed in an upper silicon surface and a source conductive layer is deposited to electrically contact a source region while a gate conductive layer is deposited atop a gate oxide layer.
U.S. Pat. No. 5,229,315, issued Jul. 20, 1993 to Jun et al., discloses a method for forming an isolated film on a semiconductor device comprising the steps of: forming a deep and narrow cylindrical groove in a substrate; filling up the groove with an oxide film, and oxidizing a polysilicon layer encircled by the groove, thereby forming an isolated film in the shape of a cylinder.
U.S. Pat. No. 5,318,665, issued Jun. 7, 1994 to Oikawa, discloses a reactive ion etch method which uses a mixed gas of HBr and Ar (10 to 25%) or a mixed gas of HBr, Ar (5 to 25%) and O
2
(0.2 to 2%) in etching a polysilicon film having a large step difference.
U.S. Pat. No. 5,656,535, issued Aug. 12, 1997 to Ho et al, discloses a simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench, the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material. The disclosure of this patent is hereby incorporated by reference herein in its entirety.
European Patent Publication Nos. 0272143 and 0565212, published Jun. 22, 1988 and Oct. 13, 1993, and assigned to the assignee of the present invention, disclose a process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry. The disclosure of these patent publications are hereby incorporated by reference herein in their entireties.
European Patent Publication No. 0821409, published Jan. 28, 1998, by Coronel et al., discloses a collar etch method for a DRAM cell. In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. In a conventional fabrication process, a Si
3
N
4
pad layer is deposited onto the bare silicon substrate, then patterned. Next, deep trenches are formed in the substrate by dry etching. An ONO layer is conformally deposited into the trenches. The trenches are filled with undoped polysilicon. About 2.5 &mgr;m of undoped polysilicon is removed from the trench in a plasma etcher. A TEOS SiO
2
collar layer is conformally deposited, then anisotropically dry etched to leave only the so-called collar. Because trenches are present at the substrate surface, the thickness of the TEOS SiO
2
collar is not uniform. The above-referenced patent publication proposes a highly selective dry etch method to anisotropically etch the TEOS SiO
2
collar while preserving the Si
3
N
4
pad layer thickness uniformity. A chemistry having a high TEOS SiO
2
/Si
3
N
4
selectivity (i.e., which etches TEOS SiO
2
faster than Si
3
N
4
by a factor of at least six) is used to etch the TEOS SiO
2
collar layer. C
4
F
8
/Ar and C
4
F
8
/Ar/CO mixtures which have respective selectivities approximately equal to 9:1 and 15:1 (depending on gas ratios) are said to be adequate in all respects. When the surface of the Si
3
N
4
pad layer is reached (this can be accurately detected), the etch is continued by an overetch of the TEOS SiO
2
layer to ensure a complete removal of the horizontal portions thereof. The disclosure of this patent publication is hereby incorporated by reference herein in its entirety.
European Patent Publication No. 0822593, published Feb. 4, 1998, by Haue et al., discloses a method of forming field effect transistors (FETs) on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide.
Masasaki Sato et al. (
Jap. J Appl. Phys
., Vol. 30, No. 7, pp. 1549-1555, April 1991) disclose the effect of gas species on the depth reduction in silicon deep submicron trench reactive ion etching. In silicon deep submicron trench reactive ion etching, a clearly larger microloading effect is found in fluorinated gas than in chlorinated gas. It was noted that adoption of a heavier halogen for the etching gas offers one way to eliminate the microloading effect because ion-assisted etching is dominant in heavier halogen etching.
Geun-Young Yeom et al. (
J. Electrochem. Soc
., Vol. 139, No. 2, pp. 575-579, February 1992) disclose a polysilicon etchback plasma process using HBr, Cl
2
, and SF
6
gas mixtures for deep trench isolation. A controllable trench polysilicon etchback profile with smooth surface and curvature was obtained by using 60 sccm HBr and 50 sccm Cl
2
gas mixture with 6 sccm SF
6
gas flow.
Commonly assigned, copending U.S. application Ser. No. 09/144,008, filed Aug. 31, 1998, by Lill et al., discloses a process for controlling the shape of the etch front in polysilicon etching applications, and a method for performing recess etchback of a polysilicon-filled trench formed in a substrate. Also disclosed is a method for forming a polysilicon-filled trench capacitor in a single-crystal silicon substrate, the trench capacitor including a dielectric collar and a buried strap. The method comprises a series of steps in which a semiconductor structure having an initial trench therein is the starting substrate.
The trench structure includes a single-crystal silicon substrate, at least one gate dielectric layer overlying a surface of the substrate, and at least one etch barrier layer overlying the gate dielectric layer. In the first step of the method, a conformal dielectric film is formed over the etch barrier layer and the sidewall and bottom of the trench. A layer of polysilicon is then applied to fill the trench. The polysilicon is then isotropically etched back to a predetermined depth within the trench using a plasma produced from a plasma source gas comprising a reactive species which selectively etches polysilicon. The plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof. After the polysilicon etchback, a collar is formed by application of a conformal layer of silicon oxide over the etch barrier layer, the sidewall of the trench, and the portion of the polysilicon which was exposed during the etching step. The silicon oxide collar is then anisotropically etched back to a first depth to expose the underlying polysilicon. The trench is then refilled with polysilicon. The polysilicon is subsequen

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