Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2003-01-06
2004-10-12
Versteeg, Steven (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192120, C427S402000, C427S331000, C216S039000, C216S041000, C134S001100
Reexamination Certificate
active
06802945
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of sputtering metal onto structures.
BACKGROUND OF THE INVENTION
Electrical isolation between two conductive structures, such as metal lines or metal bumps, will not be good in current integrated circuit (IC) without planarization. The electrical isolation problem is caused by re-deposition of conductive material/metal from the wafer holder during pre-sputter cleaning forming stringers between adjacent metal conductive structures causing electrical shorting between the structures.
U.S. Pat. No. 4,704,301 to Bauer et al. describes a metal (e.g. aluminum) coater wafer holder.
U.S. Pat. No. 6,267,852 B1 to Givens et al. describes a wafer holder in a sputter clean tool and method.
U.S. Pat. No. 6,340,405 B1 to Park describes a wafer holder in an etch tool.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide improved methods of reducing electrical shorting between adjacent conductive structures formed with a pre-sputtering cleaning step.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a wafer holder within a chamber is provided with the chamber having inner walls. The wafer holder and the inner walls of the chamber are coated with a seasoning layer. The seasoning layer being comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer is placed upon the seasoning layer coated wafer holder. The wafer including two or more wafer conductive structures thereover. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over at least over the wafer and the wafer conductive structures. The wafer is removed from the chamber. A patterned masking layer is formed over the metal barrier layer, leaving first exposed portions of the metal barrier layer. Using the patterned masking layer as masks, at least two adjacent upper metal structures are formed over the first exposed portions of the metal barrier layer. The patterned masking layer is removed, exposing second exposed portions of the metal barrier layer adjacent the at least two adjacent upper metal structures. The second exposed portions of the metal barrier layer are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process. The metal barrier layer etch process also etching and removing the exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
REFERENCES:
patent: 4704301 (1987-11-01), Bauer et al.
patent: 6080529 (2000-06-01), Ye et al.
patent: 6267852 (2001-07-01), Givens et al.
patent: 6340405 (2002-01-01), Park
patent: 6566270 (2003-05-01), Liu et al.
Chou Chien-Kang
Lin Ching-San
Liu Hsien-Tsung
Ackerman Stephen B.
Megic Corporation
Saile George O.
Stanton Stephen G.
Versteeg Steven
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