Method of metal/polysilicon gate formation in a field effect tra

Details Method of metal/polysilicon gate formation in a field effect tra Method of metal/polysilicon gate formation in a field effect tra

1998-12-07

2000-01-18

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438592, 438678, H01L 2128, H01L 21335

Patent

active

06015747&

ABSTRACT:
A method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) of the semiconductor substrate adjacent to the source and drain regions. A masking layer (136) is formed, covering substantially all the semiconductor substrate. Portions of the masking layer are then selectively removed to expose at least selected portions of the polysilicon gate. Selected portions of the polysilicon gate are partially etched. By selective electroless metal deposition, a metal layer (146) is formed on the etched selected portions of the polysilicon gate. In an alternative embodiment, the masking layer is removed before selective deposition of the electroless metal, so that electroless metal is simultaneously deposited on the polysilicon gate and the source region and the drain region.

REFERENCES:
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patent: 5268330 (1993-12-01), Given et al.
patent: 5342806 (1994-08-01), Asahina
Advanced Metallization and Interconnect Systems for ULSI Applications in 1997 by S. Lopatin Y. Shacham-Diamond, V. Dubin, P.K. Vasudev, Y. Kin, T. Smy, Oct. 21-22, 1997, MRS, pp. 437-443.
Selective electroless Ni deposition onto Pd-activated Si for integrated circuit fabrication by V.M. Dubin, S.D. Lopatin and V.G. Sokolov, Apr. 29, 1992, Thin Solid Films, vol. 226, pp. 94-98.

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