Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2002-10-31
2003-12-09
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S308000, C438S514000
Reexamination Certificate
active
06660543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of measuring implant profiles using scatterometric techniques wherein dispersion coefficients are varied based upon depth.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
During the course of manufacturing integrated circuit devices, a variety of doped regions may be formed in a semiconducting substrate. Typically, these doped regions are formed by performing an ion implant process wherein a dopant material, e.g., arsenic, phosphorous, boron, boron difluoride, etc., is implanted into localized areas of the substrate. For example, for CMOS technology, various doped regions, sometimes referred to as wells, are formed in the substrate. The wells may be formed using either N-type or P-type dopant atoms. After the wells are formed, semiconductor devices, e.g., transistors, may be formed in the region defined by the well. Of course, other types of doped regions may also be formed in modern semiconductor manufacturing operations.
As modem device dimensions continue to shrink, the implant profiles of the various doped regions become very important. That is, as device dimensions shrink, parameters of the doped region, such as depth, width, dopant concentration profile, etc., become more important. Small variations in one or more of these parameters may adversely affect device performance. For example, if well implants in a given device are formed too shallow or not formed deep enough, the devices formed in the wells may exhibit excessive leakage currents.
Various parameters reflecting the profile of implanted regions, e.g., depth, have here-tofore been determined by performing a number of calculations. These calculations are typically based upon the implant energy, the type of dopant material, the implant dose and/or the angle of the implant process. Ultimately, the accuracy of these various calculations could be determined by performing destructive testing on the device after it was completed. For example, a completed device could be cross-sectioned, and the profile of the implant region of interest could be determined by observation using a tunneling electron microscope (TEM). In some cases, resistance measurements were made of a doped region. Based upon the determined resistance value, the doped region was assumed to have a given profile. Various implant region profiles were associated with various resistance levels.
The aforementioned techniques for determining profiles of implanted regions was problematic in that, in order to confirm any calculations of the profile, time-consuming destructive testing of at least some devices, either production or test devices, was required. Moreover, such destructive testing was performed at a point so far removed in time from the implantation process that the results were not readily available to enable, if desired, timely adjustment of the implant process performed on subsequently processed wafers and later processing (e.g., RTA, diffusion) of the measured wafers. Thus, there is a need for a non-destructive testing methodology for determining at least some profile parameters of an implanted region formed in a semiconducting substrate.
The present invention is directed to various methods that may solve, or reduce, at least some of the problems described above.
SUMMARY OF THE INVENTION
The present invention is directed to several inventive methods. In one illustrative embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.
In another illustrative embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating a library comprised of a plurality of created profile traces, wherein the created profile traces are representative of implant regions having varying implant profiles, and, in creating the created profile traces, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and matching the generated profile trace to at least one of the created profile traces in the library.
In yet another illustrative embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating a target profile trace that is representative of a desired profile of the implant region, wherein, in creating the target profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to the target profile trace. In further embodiments, the method comprises modifying, based upon the comparison of the generated profile trace and the target profile trace, at least one parameter of an ion implant process used to form implant regions on subsequently processed substrates.
REFERENCES:
patent: 6104486 (2000-08-01), Arimoto
patent: 6304999 (2001-10-01), Toprac et al.
patent: 6352876 (2002-03-01), Bordogna et al.
patent: 6433878 (2002-08-01), Niu et al.
patent: 2002/0135781 (2002-09-01), Singh et al.
Lensing Kevin R.
Nariman Homi E.
Reeves Steven P.
Stirton James Broc
Advanced Micro Devices , Inc.
Chaudhari Chandra
Williams Morgan & Amerson P.C.
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