Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-03
2007-04-03
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C257S213000, C257SE27155
Reexamination Certificate
active
10538212
ABSTRACT:
A method of making a trench MOSFET includes forming a nitride liner50on the sidewalls28of a trench and a plug of doped polysilicon26at the bottom of a trench. The plug of polysilicon26may then be oxidised to form a thick oxide plug30at the bottom of the trench whilst the nitride liner50protects the sidewalls28from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
REFERENCES:
patent: 6326261 (2001-12-01), Tsang et al.
patent: 6331467 (2001-12-01), Brown et al.
patent: 6444528 (2002-09-01), Murphy
patent: 6709912 (2004-03-01), Ang et al.
patent: 0801426 (1997-10-01), None
patent: 0801426 (1997-10-01), None
patent: 0801426 (1997-10-01), None
patent: WO0072372 (2000-11-01), None
Hijzen Erwin A.
Hueting Raymond J. E.
In't Zandt Michael A. A.
Geyer Scott B.
NXP B.V.
Ullah Elias
Zawilski Peter
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