Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-02
2008-12-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07472364
ABSTRACT:
A method for matching patterns, based on an orthogonal sub-space projection of layout shapes using Walsh patterns, performs a preliminary density feature extraction of a circuit design layout, allows a user to define a pattern, and performs a high resolution search of the layout to locate all instances of the pattern. A sorted list of layout windows ranging from the most similar to quantitatively less similar is generated. The method for matching patterns significantly reduces false positives in comparison with the prior art and enables the same density data to be reused as a window is stepped in small increments across the layout.
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Lehner Timothy S.
Lehner Valerie D.
Cantor & Colburn LLP
Chiang Jack
International Business Machines - Corporation
Schnurmann H. Daniel
Tat Binh C
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