Method of mapping logic failures in an integrated circuit die

Details Method of mapping logic failures in an integrated circuit die Method of mapping logic failures in an integrated circuit die

2006-01-10

2006-01-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06986112

ABSTRACT:
A method of mapping logic failures in an integrated circuit die includes generating a navigation map of test paths for an integrated circuit die, selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths, and calculating a value for each of the cell locations that is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.

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