Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-07-09
2002-09-03
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S761000, C438S787000, C438S763000
Reexamination Certificate
active
06444508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a thin film transistor for use in an active matrix liquid crystal display panel, an input/output device as of a contact-type image sensor, a portable electronic instrument, etc., and also to a method for manufacturing such thin film transistor.
2. Description of the Related Art:
In forming a thin film transistor (hereinafter also called TFT) on a substrate of glass, the hydrogenated amorphous silicon semiconductor TFT technology and the polysilicon TFT technology are currently available as typical technologies. According to the former, the maximum temperature of the fabrication process is about 300° C., and a carrier mobility of approximately 1 cm
2
/Vsec is obtained. According to the latter, using a high-temperature process analogous to the LSI process of about 1000° C. using a substrate as of quartz, a carrier mobility of 30 to 100 cm
2
/Vsec can easily be obtained. In case of the high carrier mobility, when the thin film transistor is applied to, for example, a liquid crystal display, it is possible to simultaneously form on the same glass substrate a pixel TFT driving each pixel and even a peripheral driving circuit section as well. The resulting thin film transistor is inexpensive and small-sized.
However, in the polysilicon TFT technology, inexpensive low-melting-point glass, which is originally suitable to the former process, cannot be employed in the above-mentioned high-temperature process. For decreasing the temperature of the polysilicon TFT process, the laser crystallization technology, the low temperature film (gate insulating film) formation technology and the-low temperature interface (of insulating film and silicon) formation technology are sought after. Studies and developments have been made to solve the foregoing problems. To this end, IEEE ELECTRON DEVICE LETTERS, Vol. 15, No. 2, page 69, “High Performance Polycrystalline Silicon Thin Film Transistor Fabricated Using Remote Plasma CVD of SiO
2
,” (M. Sekiya, et al.) discloses a hybrid fabricating apparatus and method composed of two different fabrication processes: the laser crystallization for forming a good interface between an insulating film and a silicon layer at low temperature, and the remote plasma CVD for forming a silicon dioxide film. This hybrid concept aims to maintain a good insulating-film-and-silicon interface at low temperature by forming a gate insulating film on a high-quality polysilicon film, which is formed by the excimer laser crystallization without exposure to atmosphere, and by keeping the interface well clean. In this technological paper, as a polysilicon TFT fabrication process, the following process flow was proposed. After a source-and-drain layer (20 nm thick) has been formed in an island shape, a silicon layer (20 nm thick) is formed. Then, laser crystallization, hydrogen treatment (which comes immediately after laser crystallization) and fabrication of a first insulating film (SiO
2
, 100 nm thick) take place in succession. As a result, a good insulating-film-and-silicon interface is obtained at low temperature. After that, the silicon layer is patterned in an island shape. In addition, a second insulating film (100 nm thick) is formed to secure silicon-electrode isolation.
In the meantime, as reduction of the power output and the driving voltage of a liquid display, an image sensor or the like has been practical, it is increasingly becoming necessary not only to improve the performance of TFT by cleaning the interface but also to reduce the operating threshold voltage of TFT. And it has turned out from recent studies that thinning the gate insulating film is effective for reduction of the operating threshold voltage; such thinning method applied to a planar thin film transistor will now be described with reference to FIGS.
9
(
a
) to
9
(
c
) of the accompanying drawings. FIG.
9
(
a
) is a top plan view of the planar thin film transistor, FIG.
9
(
b
) is a cross-sectional view taken alone line A-A′ of FIG.
9
(
a
), and FIG.
9
(
c
) is a cross-sectional view taken along line B-B′ of FIG.
9
(
a
). A first insulating film
5
patterned in an island shape is located on and formed continuously with a semiconductor layer, which is adapted to be formed into a source-and-drain region
3
,
4
and a channel region
2
, and then a second insulating film
6
and a gate electrode (hereinafter also called simply the gate)
7
are located over the first insulating film
2
so as to cover the semiconductor layer and the island of the first insulating film
5
. Now for reducing the threshold voltage as mentioned above, it becomes necessary to reduce the total thickness of the two-layer gate insulating film
5
,
6
. This is because reduction of the two layers increases the capacitance so that an adequate electric field effect can be obtained even at low voltage. Whereas the semiconductor layer, unlike the gate insulating film, cannot be thinned, partly because it should be doped with an impurity as by ion implantation and partly because an adequate process margin during laser crystallization should be secured. Consequently, if the gate insulating film is thinned in order to lower the threshold voltage as mentioned above, then the thickness of the second gate insulating film becomes smaller than the difference between the semiconductor layer and the first gate insulating film so that gate-leak-free covering is difficult to achieve. Thus short circuit (gate leak) would tend to occur between the gate and the source-and-drain region.
As a solution for these problems, the following method was proposed by Japanese Patent Laid-Open Publication No. Hei6-85258. As shown in
FIG. 10
of the accompanying drawings of the present specification, a semiconductor film
12
is formed in an island shape on an insulator substrate
11
and then a first insulating film
13
is formed on the island-shape semiconductor film
12
, whereupon a second insulating film
21
is formed so as to cover the stepped peripheral edges of such composite island of the semiconductor film
12
and first insulating film
13
. And a gate electrode
14
is formed over the first insulating film
13
surrounded by the second insulating film
21
, so the semiconductor film
12
and the gate
14
are perfectly isolated from each other, preventing occurrence of short circuit (gate leak) between the semiconductor film
12
and the gate
14
, i.e., between the gate and the source-and-drain. To realize such structure, the second insulating film
21
has to be etched selectively, namely, at only the region directly above the island after having been formed along its entire surface over the first insulating film
13
. As a consequence, the second insulating film
21
requires a material such that it can be selectively etched with respect to the first insulating film
13
or the second insulating film
21
requires a selective etching process. Especially when the first insulating film
13
is thinned further in an effort to improve the throughput and performance, a much higher selective ratio is needed, and a dry etching method free of plasma damage to either the gate insulating film or insulating film and semiconductor interface would be necessitated.
As an alternative method that ensures inter-electrode isolation using a two-layer insulating film, Japanese Patent Laid-Open Publication No. Hei6-61490 discloses a conventional two-layer technology which optimizes the thickness and cross-sectional shape of each layer and employs two highly dielectric thin films for securing high performance of a thin film transistor. As shown in
FIG. 11
, this conventional method aims to provide a well-insulating, highly reliable isolation structure by optimizing the shape of a second insulating film
1014
b
rather than the shape of a first insulating film
1014
a
, which covers gates
103
a
,
1013
b
. Further, the gate metal as a prospective lower electrode is covered with tungsten oxide and then a silicon nitride film for forming a good MIS interface w
Okumura Hiroshi
Sato Yoshinobu
Tanabe Hiroshi
Yuda Katsuhisa
Russell Volita
Trinh Michael
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