Method of manufacturing the array substrate capable of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S155000, C438S280000, C257SE21586, C257SE21409

Reexamination Certificate

active

08058114

ABSTRACT:
A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

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patent: 7057675 (2006-06-01), Ha
patent: 7541212 (2009-06-01), Oh
patent: 2002/0036724 (2002-03-01), Ha
patent: 2004/0201019 (2004-10-01), Kim et al.
patent: 2008/0115718 (2008-05-01), Kim et al.
patent: 2009/0117333 (2009-05-01), Lee et al.
patent: 2009/0159944 (2009-06-01), Oh
patent: 2009/0166635 (2009-07-01), Kim et al.
patent: 2009/0184324 (2009-07-01), Oh et al.

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