Method of manufacturing spacer etch mask for...

Details Method of manufacturing spacer etch mask for... Method of manufacturing spacer etch mask for...

2001-06-20

2002-10-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000

Reexamination Certificate

active

06465303

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to fabricating SONOS type nonvolatile memory devices. In particular, the present invention relates to improved methods of fabricating spacers in SONOS type nonvolatile memory devices.
BACKGROUND ART
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), employ a memory cell characterized by a vertical stack of a tunnel oxide, a first polysilicon layer over the tunnel oxide, an ONO (oxide-nitride-oxide) interlevel dielectric over the first polysilicon layer, and a second polysilicon layer over the ONO interlevel dielectric. For example, Guterman et al (IEEE Transactions on Electron Devices, Vol. 26, No. 4, p. 576, 1979) relates to a floating gate nonvolatile memory cell consisting of a floating gate sandwiched between a gate oxide and an interlevel oxide, with a control gate over the interlevel oxide.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate “hot ” (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Subsequently, SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices have been introduced. See Chan et al, IEEE Electron Device Letters, Vol. 8, No. 3, p. 93, 1987. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. Since the electrical charge is trapped locally near whichever side that is used as the drain, this structure can be described as a two-transistor cell, or two-bits per cell. If multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend increasing the amount of information held/processed on an integrated circuit chip.
For simplicity, a two-bit per cell implementation of SONOS is described. While both bits of SONOS type memory devices are programmed in a conventional manner, such as using hot electron programming, each bit is read in a direction opposite that in which it is programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded or at a lower voltage. Hot electrons are accelerated sufficiently so that they are injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it is written, meaning voltages are applied to the gate and the source while the drain is grounded or at a lower voltage. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one of the bits leaves the other bit with its information intact and undisturbed.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that the potential drop across the portion of the channel beneath the trapped charge region is significantly reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits much faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus unprogrammed states remains the same as when the device is read in the forward direction.
SONOS type memory devices offer additional advantages as well. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage includes reduced wear out from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprogrammed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell. Although there are advantages associated with SONOS type non-volatile memory devices, there are disadvantages as well. In many instances, it is desirable to form gate transistors in the periphery region with source and drain regions possessing both lightly doped areas and heavily doped areas. This is accomplished by forming spacers adjacent the transistors on the substrate. However, when forming spacers adjacent the memory cells and various gate transistors in the periphery, damage to device often results. This includes damage to the substrate as well as damage to the ONO dielectric layer in the core region. Such damage may cause leakage currents within the device.
For example, referring to prior art
FIG. 1
, a nonvolatile memory substrate
12
is provided having a core region
14
and a periphery region
16
. An ONO dielectric
17
is positioned in the core region
14
over the substrate
12
. Flash memory cells
18
are positioned in the core region
14
while gate transistors
20
, such as input/out devices, are positioned in the periphery region
16
. A spacer material
22
is deposited over the substrate
12
. There is extra space
24
between some of the memory cells
18
to subsequently provide for a contact opening.
Referring to prior art
FIG. 2
, a portion of the spacer material
22
is etched to form spacers
30
adjacent the memory cells
18
and the gate transistors
20
. However, in some instances when etching a portion of the spacer material
22
, damage
26
to the substrate
12
results and/or damage
28
to the ONO dielectric
17
results. Reliability of the resultant devices is decreased when there is damage
28
to the ONO dielectric
17
. And damage
26
to the substrate
12
often creates an

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