Method of manufacturing semiconductor memory device having a cap

Details Method of manufacturing semiconductor memory device having a cap Method of manufacturing semiconductor memory device having a cap

1997-06-24

1998-08-11

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, H01L 218242

Patent

active

057926913

ABSTRACT:
A method of manufacturing a semiconductor memory device, having the steps of: forming field oxide films in isolation regions on a surface of a p-type silicon substrate, forming a first interlevel insulating film consisting of a silicon oxide film; forming, on a surface of said first interlevel insulating film, bit lines; forming a second interlevel insulating film consisting of a silicon oxide film; forming bit contact holes through the second and first interlevel insulating films, and node contact holes through the second and first interlevel insulating films; forming a photoresist film pattern on a surface of said n.sup.+ -type poly-Si film; forming poly-Si film; contact plugs, and plug loss portions in which no contact plug is filled; forming an insulating film spacers covering side surfaces of said storage node electrodes, and insulating film caps filled in the plug loss portions; and forming a capacitor insulating film and a cell plate electrode.

REFERENCES:
patent: 5387533 (1995-02-01), Kim
patent: 5409855 (1995-04-01), Jun
patent: 5629539 (1997-05-01), Aoki et al.
A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-grain Storage Node for 64Mb DRAMS, M. Sakao et al., International Electronic Devices Meeting, San Francisco, CA, Dec. 9-12, 1990, pp. 27.3.1-27.3.4.

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