Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-09
2001-12-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000, C438S302000
Reexamination Certificate
active
06329250
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor memory device, and more particularly to a mask ROM including a memory transistor to which data is fixedly written as a difference between threshold voltages depending on an existence and non-existence of a doped channel layer.
A mask ROM in which data are fixedly stored by mask programing has hitherto been known as a read-only semiconductor memory. The mask ROM may be functionally structured so that an indication of whether or not the memory transistor is disposed at an intersection between a bit line and a word line is set corresponding to data “
1
” or “
0
”. A diffused layer program mode shown in
FIG. 19 and a
contact program mode shown in
FIG. 20
have been used as a programing mode of the mask ROM having a comparatively small memory capacity.
A mask ROM in which data are fixedly stored by mask programming has hitherto been known as a read-only semiconductor memory. The mask ROM may be functionally structured so that an indication of whether or not the memory transistor is disposed at an intersection between a bit line and a word line is set corresponding to data “
1
” or “
0
”. A diffused layer program mode shown in
FIG. 19 and a
contact program mode shown in
FIG. 20
have been used as a programming mode of the mask ROM having a comparatively small memory capacity.
Referring to
FIGS. 19 and 20
, a region indicated by hatching is a device isolation region, and a memory transistor MC corresponds to an intersection between a word line WL and a bit line BL. According to the diffused layer program mode in
FIG. 19
, the data is written depending on whether a diffused layer is formed at the area of the memory transistor which is surrounded by a broken line. According to the contact program mode in
FIG. 20
, the data is written depending on whether or not a bit line contact of the memory transistor MC surrounded by a broken line is formed. Both cases take a NOR type cell structure in terms of an equivalent circuit as shown in FIG.
21
.
In the diffused layer program mode, though capable of enhancing integration, the diffused layer is formed at an initial stage of a process of manufacturing the memory, and hence a TAT (Turn Around Time) elongates. The contact program mode, because of being a program after forming the device, has a shorter TAT than in the diffused layer program mode but less integration.
By contrast, a NAND type cell shown in
FIGS. 22 and 23
is used as the mask ROM capable of enhancing the integration. A region indicated by hatching in
FIG. 22
is a device isolation region, wherein the memory transistors are connected in series to the bit line. The programming is executed depending on whether channel ion implantation is performed beforehand into a memory transistor MC region defined by a broken line. For example, the memory transistor formed with a doped channel layer is categorized as a depletion (D) type, the memory transistors other than the D-type are classified as an enhancement (E) type. It follows,
as shown in
FIG. 23
, that the data is written as a distribution of the E- and D-types.
A cell structure of the large-capacity mask ROM includes a contactless type cell shown in
FIG. 24
in addition to the NAND type cell. The contactless type cell is obtained by providing n
+
type diffused layers in strips on the semiconductor substrate, thereafter providing a gate oxide layer over the entire surface, and pattern-forming word lines WL thereon by using polysilicon layers. Three strips of adjacent n
+
type diffused layers become, as illustrated in
FIG. 24
, a bit line BL and ground lines VSSO, VSSl between which the bit line BL is interposed. All the regions just under the word lines interposed between the n
+
type diffused layers serve as channel regions of the memory transistors. The data is written depending on whether ion implantation into the channel region of one single memory transistor indicated by the broken line is performed or not.
There were, however, limits to the high integrations of the mask ROMs of the NAND type cell and of the contactless type cell. A major factor therefor is that the channel ion implantation of the memory transistor might involve a deviation in mask alignment, and hence a design rule for the channel ion implantation must have some allowance. Therefore, if the memory transistor is downsized, a lower limit of a memory cell size is resultantly specified by the design rule for the channel ion implantation, and a further downsized structure is hard to obtain.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a semiconductor memory device for executing programming by a channel ion implantation and a manufacturing method thereof, which are capable of reducing a cell size by making a doped channel layer of a memory transistor self-aligned with a gate electrode.
According to one aspect of the present invention, there is provided a semiconductor memory device comprising:
a semiconductor substrate;
a plurality of memory transistors for storing fixed data, each having a gate electrode, a source diffused layer and a drain diffused layer, provided in an array on said semiconductor substrate;
wherein the fixed data of a memory transistor is determined by existence or non-existence of a doped channel layer under the gate electrode, and the doped channel layer extends to at least one of the source and the drain diffused layers so that the doped channel layer overlaps with at least one of the source and the drain diffused layers.
In this semiconductor memory device, the doped channel layer is formed deeper than the source/drain diffused layers so as to be overlapped by one of the source/drain diffused layers and not to be overlapped with the other diffused layer. A punch-through phenomenon between the source/drain diffused layers can be thereby surely prevented.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising the steps of:
forming a plurality of memory transistors, each having a gate electrode on a semiconductor substrate, each of said transistors having a source diffused layer and a drain diffused layer;
providing a mask having an opening formed so that a side surface of the gate electrode and substrate surface of one of the source diffused layer and the drain diffused layer are exposed; and
providing a doped channel layer under the gate electrode and in one of the source and drain diffused layers by implanting impurity ions through said opening with an inclined angle selected from a range from perpendicularity to parallelism to said semiconductor substrate.
According to the present invention, there are a case (a) where the memory transistor is classified as a first conductivity type MOS transistor, and the doped channel layer is categorized as a second conductivity type impurity layer, and a case (b) where the memory transistor is classified as the first conductivity type MOS transistor, and the doped channel layer is categorized as a first conductivity type impurity layer. In the case (a), the memory transistor formed with the doped channel layer has a higher threshold value than in the memory transistor in an initial state. To be specific, for instance, the memory transistor in the initial state is, it is assumed, of a D-type, and the memory transistor provided with the doped channel layer is set into an E-type. In the case (b), the threshold value of the memory transistor provided with the doped channel layer becomes lower than in the memory transistor in the initial state. Specifically, for example, it is assumed that the memory transistor in the initial state is of the E-type, and the memory transistor provided with the doped channel layer is set into the D-type.
According to the present invention, the ion implantation for forming the doped channel layer with an inclined angle may be effected either from the side of a source diffused layer or from the side of a drain diffused layer. In the case (a), h
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Tsai Jey
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