Method of manufacturing semiconductor integrated circuit device

Details Method of manufacturing semiconductor integrated circuit device Method of manufacturing semiconductor integrated circuit device

2003-04-23

2004-10-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C365S185240

Reexamination Certificate

active

06800524

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit device incorporating an on-chip ROM to which data is written during a manufacturing process.
2. Description of Conventional Embodiment
FIG. 4
is a block diagram showing a semiconductor integrated circuit device, and includes a mask ROM
1
, and a block
2
, a block
3
and a block
4
having arbitrary functions. In addition, in this conventional example, it is assumed that the semiconductor integrated circuit device has five metal interconnection layers.
FIG. 5A
is a top view of a memory cell of the mask ROM
1
configuring the semiconductor integrated circuit device of
FIG. 4
, and
FIG. 5B
is a sectional drawing taken on a chain line E—E of FIG.
5
A.
In FIG.
5
A and
FIG. 5B
, SUB is a semiconductor substrate on which the mask ROM
1
and the blocks
2
-
4
in
FIG. 4
are formed, G is a gate of an N-channel transistor which is a memory cell transistor, D is a drain of the N-channel transistor, S is a source of the N-channel transistor, Z
1
, Z
2
, Z
3
, Z
4
, Z
5
are a first, a second, a third, a fourth, a fifth layers of interlayer dielectric (hereinafter referred to as ILD) layers, V
1
, V
2
, V
3
, V
4
, V
5
are via holes formed in the ILD layers Z
1
, Z
2
, Z
3
, Z
4
, Z
5
, respectively, and M
1
,M
2
,M
3
,M
4
,M
5
are a first, a second, a third, a fourth, a fifth layer of metal interconnection layers. Pads are formed by the metal interconnection layers M
1
, M
2
, M
3
, and M
4
herein and a bit line is formed by the metal interconnection layer M
5
. Hereinafter, M
1
,M
2
,M
3
, and M
4
are also referred to as pads and M
5
, as a bit line. U-BIT and B-BIT show memory cell regions, each of which is 1 bit. The drain D is connected to the bit line M
5
through the metal pads M
1
, M
2
, M
3
, and M
4
, and the via holes V
1
, V
2
, V
3
, V
4
, V
5
.
A description will be made of the memory cell of the mask ROM in the semiconductor integrated circuit device configured as above.
The mask ROM makes “discharging” or “not discharging” an electric charge stored in the bit line through the transistor arranged in each bit correspond to “0” and “1” of stored data, respectively, and determines “discharging” or “not discharging” by “connecting” or “not connecting” the bit line to the transistor of each bit in manufacturing steps, respectively.
In addition, because data writing of the mask ROM is performed in the manufacturing steps, and it is strongly required from the market to deal, for a short period, with data changes etc. caused by specification changes or the like of the semiconductor integrated circuit device, it is also necessary to form the mask ROM by interconnection layers of the memory cell equivalent to the interconnection layers of the other blocks
2
,
3
, and
4
of the semiconductor integrated circuit device, and to write the memory data in an upper layer as much as possible.
In order to satisfy these requirements, the memory cell of the conventional mask ROM is configured using the same five interconnection layers M
1
-M
5
as the other blocks
2
,
3
, and
4
of the semiconductor integrated circuit device in
FIG. 4
, a fifth layer of the uppermost layer is configured to be the bit line, in the manufacturing process of forming the via hole V
5
in the uppermost layer for connecting the bit line M
5
to the drain D, the state of “connecting” or “not connecting” the bit line to the transistor of each bit is created by “forming” or “not forming”, and is made to correspond to “0” or “1” of each stored data.
The conventional semiconductor integrated circuit device described above has the following problems.
In recent years, while the semiconductor integrated circuit device is being multi-layered, in order to shorten a manufacturing TAT (Turn Around Time) when changing the data to be stored, it is also necessary for the memory cell of the mask ROM in the semiconductor integrated circuit device to be multi-layered, and since the more multi-layered, the more the manufacturing process of the memory cell increases, the probability of occurrence of failures increases, resulting in decreasing yield of the semiconductor integrated circuit device.
BRIEF DESCRIPTION OF THE INVENTION
The present invention is to resolve the problems in a conventional semiconductor integrated circuit device described above, and the object is to provide a method of manufacturing the semiconductor integrated circuit device capable of shortening a manufacturing TAT when changing data to be stored in a mask ROM, and increase a manufacturing yield.
According to the present invention, in the method of manufacturing the semiconductor integrated circuit device, a mask ROM cell array portion is provided in a predetermined region of the semiconductor substrate, on the surface of which a plurality of insulating layers and interconnection layers are alternately stacked, respectively, the mask ROM cell array portion comprises, a plurality of memory cell transistors formed in a predetermined region of the semiconductor substrate lower than the insulating layers and the interconnection layers, and a bit line formed by a predetermined interconnection layer among the interconnection layers, wherein when a first data is written to each of the memory cell transistors, the bit line and the memory cell transistors are made to be in an electrically connected state through a via hole for use in data writing by forming the via hole for use in data writing in the insulating layer just below the bit line, and when a second data is written, the bit line and the memory cell transistor are made to be in an electrically disconnected state by not forming a via hole for use in data writing, and wherein, during the fabrication of samples or prototypes of the semiconductor integrated circuit device, the bit line is formed by a first interconnection layer upper than a lowermost layer among a plurality of interconnection layers, and during the manufacture of mass-produced products of the semiconductor integrated circuit device, the bit line is formed by a second interconnection layer lower than the first interconnection layer among the plurality of interconnection layers.
In accordance with this manufacturing method, when fabricating the samples or the prototypes where data writing to the mask ROM of the semiconductor integrated circuit device is frequently changed, by means of forming the bit line by an upper interconnection layer, and configuring the insulating layer just below it as a forming layer of the via hole for use in data writing, the manufacturing TAT of the semiconductor integrated circuit device is shortened, while when manufacturing mass-produced products after ROM data is determined, by means of forming the bit line by a lower interconnection layer and configuring an insulating layer just below it as a forming layer of the via hole for use in data writing, it is possible to decrease manufacturing process steps of the memory cell by reducing the number of the layers configuring the memory cell, and to improve a manufacturing yield of the semiconductor integrated circuit device.
In this case, when manufacturing mass-produced products, the via hole may not be formed in the insulating layer just above the bit line over the region of the mask ROM cell array portion, or the via hole may not be formed in the insulating layer upper than the bit line over the region of the mask ROM cell array portion, either. Alternatively, the interconnection layers upper than the bit line may not be formed over the region of the mask ROM cell array portion, and the via hole may not be formed in the insulating layer upper than the bit line, either.
In addition, in accordance with an aspect of the present invention, when manufacturing mass-produced products, as a mask pattern for a mask used for forming the via hole for use in data writing, using substantially the same mask pattern as the mask pattern used for forming the via hole for use in data writing of the samples or the prototyp

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