Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-30
2002-07-23
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S981000
Reexamination Certificate
active
06423588
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, the invention relates to a technique that is effective and useful when applied to a semiconductor integrated circuit device that has capacitive elements, each comprising a MISFET (Metal Insulator Semiconductor Field Effect Transistor).
BACKGROUND OF THE INVENTION
A method is known in which capacitive elements are formed in an LSI comprising MISFETs that compose circuits, by utilizing the gate oxide films of the MISFETS. To use the capacitance of the gate oxide film of each MISFET, the storage region of a p-channel MISFET or the inversion region of an n-channel MISFET is utilized.
The Japanese Patent Application Laid-open Publication No. 61-232656 discloses the technique of forming a MOS-type capacitive element at the same time the thin gate oxide film of a nonvolatile memory element is formed, thereby to reduce the area of the MOS-type capacitive element. This technique has been devised in view of the fact that the electrode of a MOS-type capacitive element is necessarily large if the insulating film of the MOS-type capacitive element is formed at the same time the gate oxide film of an ordinary MOSFET is formed, because the gate oxide film of the MOSFET is relatively thick.
The Japanese Patent Application Laid-Open Publication No. 5-235289 discloses an LSI in which the MOS-type capacitive elements are used in an inversion region over the entire input voltage range by controlling the threshold voltage (Vth) of the MOS-type capacitive elements. The LSI has been proposed in consideration of the fact that a conventional MOS-type capacitive element that uses the storage region has its operating characteristic greatly influenced if the operating power-supply voltage is lowered as required to minimize the power the LSI consumes.
SUMMARY OF THE INVENTION
In recent years, MISFETs have been made smaller and smaller. The gate oxide film of each MISFET is decreasing to 3 &mgr;m or less. If the gate oxide film thickness continues to decrease, however, the leakage current will noticeably increase due to the defects in the gate oxide film or directly due to the tunnel current. Consequently, the gate oxide film may not be able to provide stable capacitance if used as a capacitive element.
Accordingly, an object of the present invention is to provide a technique of reducing the leakage current in a capacitive element that comprises the gate oxide film of a MISFET.
Another object of the invention is to provide a technique of forming a capacitive element having a small leakage current, without increasing the number of manufacturing steps.
Additional objects and novel features of the invention will be obvious from the description, which follows, and the drawings accompanying the present specification.
The representative embodiments of this invention will be briefly described as follows.
(1) A semiconductor integrated circuit device comprising: a first MISFET having a first gate insulating film; a second MISFET having a second insulating film thinner than the first gate insulating film; and a capacitive element constituted by the first MISFET.
(2) A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first gate insulating film having a first thickness on first and second major-surface regions of a semiconductor substrate, and forming a second gate insulating film having a second thickness, smaller than the first thickness, on a third major-surface of the semiconductor substrate;
(b) forming a first conductive film including a silicon film, on the semiconductor substrate on which the first and second gate insulating films have been formed;
(c) introducing n-type impurities into a part of the silicon film and p-type impurities into another part of the silicon film;
(d) forming gate electrodes by patterning the first conductive film, thereby forming, in the first major-surface region, an n-channel MISFET having a gate electrode including an n-type silicon film and a p-channel MISFET having a gate electrode including a p-type silicon film, and forming, in the second major-surface region, a p-channel MISFET having a gate electrode including an n-type silicon film and constituting a capacitive element, and forming, in the third major-surface region, an n-channel MISFET having a gate electrode including an n-type silicon film and a p-channel MISFET having a gate electrode including a p-type silicon film.
Hence, the leakage current of the capacitive element constituted by a MISFET can be decreased since the MISFET has a thick gate insulating film.
Further, the capacitive element can have a high threshold voltage, because it is constituted by a p-channel MISFET having a gate electrode including an n-type silicon film. The capacitive element can therefore operate reliably even at a low power-supply voltage. In addition, special manufacturing steps need not be performed to increase the threshold voltage of the p-channel MISFET.
REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 5723355 (1998-03-01), Chang et al.
patent: 5847432 (1998-12-01), Nozaki
patent: 61232656 (1986-10-01), None
patent: 5-235289 (1993-09-01), None
Nonaka Yusuke
Suzuki Kazuhisa
Takahashi Toshiro
Yanagisawa Yasunobu
Antonelli Terry Stout & Kraus LLP
Chaudhari Chandra
Hitachi , Ltd.
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