Method of manufacturing semiconductor integrated circuit...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S199000, C257SE21301, C257SE21637

Reexamination Certificate

active

07109076

ABSTRACT:
Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.

REFERENCES:
patent: 2002/0004263 (2002-01-01), Tanabe et al.
patent: 2003/0003639 (2003-01-01), Kanda et al.
patent: 2004/0104416 (2004-06-01), Takaura et al.
patent: 7-161826 (1995-06-01), None
patent: 9-260509 (1997-10-01), None
patent: 10-50857 (1998-02-01), None
patent: 11-195713 (1999-07-01), None
patent: 2001-24168 (2001-01-01), None
patent: 2001-210725 (2001-08-01), None

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