Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-19
2001-05-08
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000
Reexamination Certificate
active
06228717
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing MOS (Metal Oxide Semiconductor) devices where gate electrodes are formed on a gate insulating film covering the main surface of a semiconductor substrate. More particularly, this invention relates to improvements in the shape of the gate edge portions of a gate electrode (or at least the corners on the source or drain region side where the bottom and sidewalls of a gate electrode meet each other).
In the manufacture of LSI (Large Scale Integrated) devices, the gate electrodes of MOSFETs have generally been formed by RIE (Reactive Ion Etching) techniques and then subjected to post-oxidation. Specifically, when polycrystalline silicon has been used as an electrode material, the polycrystalline silicon is left bare immediately after the gate electrodes were etched. The gate oxide film under the gate electrodes (especially near the etched sections) has been damaged during the etching. Therefore, post-oxidation is necessary to recover the gate oxide film from damage and coat the gate electrodes (polycrystalline silicon) with insulating films.
Especially in the case of a nonvolatile memory with a stacked gate structure, electric charges are retained in the floating gate electrode and the quality of the gate oxide film (or tunnel oxide film) near the gate edge portion s of the floating gate electrode has a great effect on the device characteristics. Consequently, it is important to recover the tunnel oxide film from damage by post-oxidation.
FIGS. 1A and 1B
schematically show th e processes related to post-oxidation in the manufacture of conventional MOSFETs. For example, after the processes (not shown) of forming well region and element isolating regions, a gate oxide film
101
is formed on the main surface of a semiconductor substrate
102
. After a gate electrode
103
has been formed on the gate oxide film
102
(see FIG.
1
A), post-oxidation is effected. In the post-oxidation process, an oxidizing agent
104
is applied all over the gate electrode
103
, which not only recovers the gate oxide film
102
from damage caused by the formation of the gate electrode
103
but also coats the gate electrode
103
with an insulating film
105
(see FIG.
1
B).
With the conventional MOSFET however, its structure allows the oxidizing agent
104
to be supplied sufficiently to the sidewalls of the gate electrode
103
but less sufficiently to the gate edge portions
103
a
contacting the gate oxide film
102
. In addition, the effect of stress makes the speed of oxidation at the gate edge portions
103
a
lower than the speed of oxidation at the sidewalls of the gate electrode
103
. As a result, for example, as shown in
FIG. 1B
, the insulating film
105
grows on the sidewalls of the gate electrode
103
differently from the gate edge portions
103
a
, which makes the shape of the gate edge portions
103
a
tend to sharpen. Since an electric field concentrates on the sharp portions, the gate oxide film
102
deteriorates heavily at those portions, resulting in a decrease in the reliability of the device.
In the case of NOR flash EEPROMs (Electrically Erasable Programmable Read-Only memories), stacked-gate nonvolatile memories, the controllability of the erase threshold value is important. For example, the efficiency of emitting electrons from the floating electrode to the diffused layer on the source region side depends largely on the shape of the floating gate and the thickness of the tunnel oxide film. Particularly depending on the shape of the gate edge portions of the floating gate electrode, the erasing speed (the erase threshold value) varies greatly, having an adverse effect on the operation of the device. Specifically, the data in a NOR flash EEPROM is erased by applying a strong electric field to the overlap region of the source region and the floating gate electrode and pulling electrons out of the floating gate into the source region. Therefore, when the gate edge portions of the floating gate electrode are sharp, or when the gate edge portions have a shape on which an electric field is liable to concentrate, the erase current density depends on the shape, permitting the erasing speed to vary greatly.
FIG. 2
schematically shows the configuration of a memory cell in an ordinary NOR flash EEPROM. In the cell, for example, an n-type source region
202
and an n-type drain region
203
are selectively formed at the surface of a p-type semiconductor substrate
201
. A tunnel oxide film
205
is provided above the p-type semiconductor substrate
201
and on a channel region
204
between the source region
202
and drain region
203
. On the tunnel oxide film
205
, a floating gate electrode
206
is provided. On the floating gate electrode
206
, an interlayer insulating film
207
is provided. On the interlayer insulating film
207
, a control gate electrode
208
is provided. A structure composed of the floating gate electrode
206
, control gate electrode
208
, and interlayer insulating film
207
is coated all over with an oxide film
209
.
With the memory cell in the NOR flash EEPROM constructed as described above, when the data is erased, a negative potential (e.g., −10V) is applied to the control gate electrode
208
and a positive potential (e.g., +5V) is applied to the source region
202
. Then, F-N tunnel current (indicated by a solid line
301
) flowing from the vicinity of the center of the floating gate electrode
206
extracts electrons held in the floating gate electrode
206
into the source region
202
. This erases the data.
When the gate edge portions of the floating gate electrode
206
are sharp, an electric field concentrates on the sharp gate edge portions, which permits F-N tunnel current flowing there (indicted by a broken line
302
) to increase. When the F-N tunnel current
302
is dominant over the original erase current (F-N tunnel current
301
), the erasing speed at the cell is higher than that in the other cells.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device manufacturing method capable of alleviating the concentration of an electric field on the gate edge portions of a gate electrode and thereby improving the device characteristics.
The foregoing object is accomplished by providing a method of manufacturing a semiconductor device, comprising: a first step of forming a gate electrode section on an insulating film provided on a semi-conductor substrate; a second step of forming an SiN film or an SiON film at least on a sidewall of the gate electrode section; and a third step of carrying out a thermal oxidation process after the second step to selectively promote oxidation at an edge portion of the gate electrode section adjacent to the insulating film.
With the semiconductor device manufacturing method according to the present invention, not only is the insulating film recovered from damage caused by the formation of the gate electrode section, but also an oxide film is selectively formed thicker on the gate edge sections of the gate electrode section contacting the insulating film. This enables the gate edge portions of the gate edge electrode section to be formed into a shape on which an electric field is difficult to concentrate.
Especially when a nitride film or an oxy nitride film is selectively formed, nitriding or oxy-nitriding at low temperatures for a short time enables only the polycrystalline silicon on the sidewalls of the gate electrode section to be nitrided (or oxy-nitrided) effectively, without nitriding (or oxy-nitriding) a gate insulation film.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5051794 (1991-09-01), Mori
patent: 5208174 (1993-05-01), Mor
Amemiya Kazumi
Hazama Hiroaki
Watanabe Toshiharu
Booth Richard
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
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