Method of manufacturing semiconductor devices, etching...

Details Method of manufacturing semiconductor devices, etching... Method of manufacturing semiconductor devices, etching...

2000-08-25

2002-08-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S645000, C438S745000, C438S748000, C438S756000, C438S981000, C216S038000, C216S092000, C216S099000

Reexamination Certificate

active

06436809

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabrication processes for semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices for providing the formation of tungsten plugs and polysilicon plugs, and for minimizing the step-height differences of intermediate insulating layers by etching thin films on the semiconductor substrate using a specific etching composition and spin etching method, and to an etching for manufacturing semiconductor devices, and semiconductor devices made by these processes.
DESCRIPTION OF THE RELATED ART
Recently, with semiconductor devices becoming more highly-integrated, there is an increased demand for the fine pattern formation technology of semiconductor devices and the multi-layered structure of circuit distribution.
In other words, the surface structure of the semiconductor devices are becoming more complicated, and the step-height differences between layers can cause malfunctions in the fabrication process of semiconductor devices.
Among the various fabrication processing steps, photolithography is used to form a photoresist pattern on the semiconductor substrate by coating a wafer with photoresist, aligning the wafer and a pattern mask having circuit distributions, and carrying out an exposure process by irradiating the photoresist on the wafer with light shining through the mask.
In the conventional fabrication method, the relatively-large Critical Dimension and the low-layered structure of the semiconductor devices cause few problems. However, with the finer patterns used on semiconductor substrates these days, and their multilayered structures, it is more difficult to exactly focus between the upper position and the lower position of the step-height difference in the exposure process, so that the precise pattern formation is hard to achieve.
Therefore, in order to minimize the step-height difference, the planarization technology of wafers has become more important. Conventionally, “partial planarization” has been employed for the planarization of wafers, using such methods as SOG film deposition, Etch Back, or Reflow, etc., which do not address the above problems and furthermore, cause many additional problems. As a result, “global planarization” called the Chemical Mechanical Polishing (CMP) method has been developed as a planarization process that operates throughout the whole surface of the wafer.
The CMP method planarizes the wafer surface by means of chemical and physical reaction, that is, by supplying a slurry as a thin film on a surface of the wafer having a pattern formed thereon, contacting the wafer with the polishing pad surface, causing a chemical reaction on the wafer surface, and simultaneously allowing the uneven wafer surface to be physically polished by rotating the wafer to achieve planarization.
The removal rate and the uniformity of planarization are important parameters in the CMP technology, and these are determined by the processing conditions of the CMP facility, slurry types, and polishing pad types, etc. In particular, the components, pH, and ion concentration of the slurry greatly affect the chemical reaction of the thin film.
The slurry is mainly divided into two types, oxide film slurry and metal film slurry. The oxide film slurry is alkali, and the metal film slurry is acidic.
In the case where silicon dioxide (SiO
2
) is planarized using an oxide film CMP process, the property of the silicon dioxide (SiO
2
) is changed into hydrophillic subject to H
2
O permeability by the reaction with alkali slurry. The water intruded into the silicon dioxide (SiO
2
) disconnects the connection chains of the silicon dioxide (SiO
2
). Then, the silicon dioxide (SiO
2
) is removed by the physical mechanism with the abrasive.
In the case of metal film CMP process, however, the chemical reaction on the surface of the metal film by oxidant inside the slurry creates a metal oxide film, and the metal oxide film is removed by the mechanical (physical) friction of the abrasive starting with the outermost layer of the uneven pattern.
FIG. 1
is a schematic diagram showing a conventional CMP apparatus for manufacturing semiconductor devices.
Referring to
FIG. 1
, the CMP apparatus comprises a polishing head
102
, a polishing table
104
, and a polishing pad
108
. The CMP process is carried out on the polishing table
104
. The polishing pad
108
is formed on the polishing table and holds a semiconductor substrate
100
. A slurry is then supplied from a slurry supply line
106
and is used to polish the substrate
100
. The polishing head
102
secures the substrate
100
to the polishing pad and is movable in a rotational direction.
In operation, the polishing pad
108
contacts with the semiconductor substrate
100
. The semiconductor substrate
100
is then rotated by the polishing head
102
, and the slurry is supplied on the grinding pad
108
. The slurry and the surface of the semiconductor substrate
100
then react each other, which causes the substrate to be polished by the polishing pad
108
.
FIGS. 2
to
7
are cross sectional views for manufacturing semiconductor devices in order to describe the conventional processing sequences of a tungsten plug formation. The tungsten plug portion and an align mark during the tungsten plug formation are shown simultaneously.
FIGS. 2
to
7
are divided into a cell portion (C) for the formation of the pattern element and a peripheral portion (P) for the formation of the align mark, etc.
First, as shown in
FIG. 2
, an oxide film
114
is formed as an insulator on a semiconductor substrate
110
having a plurality of local patterns
112
preformed apart from each other. The local pattern
112
can use a polysilicon pattern or a metal pattern as a conductive layer. The oxide film
114
is a silicon dioxide film (SiO
2
) formed by a conventional Chemical Vapour Deposition process. Phosphosilicate (PSG) or Borophosphosilicate (BPSG) is used as an insulating layer between the polysilicon pattern and the metal film. The oxide film
114
is formed on the align mark portion (not shown).
Then, as shown in
FIG. 3
, in the planarization step of the oxide film
114
, the oxide film
114
, which is uneven by the local pattern
112
, is planarized using the CMP apparatus shown in FIG.
1
.
Then, as shown in
FIG. 4
, in the formation of contact hole
116
, the contact hole
116
is formed via a typical photolithography and etch process by coating the oxide film
114
with photoresist and exposing the local pattern
112
and the semiconductor substrate
110
. At this time, contact holes for forming the align mark
118
are formed with a diameter bigger than that of the contact hole
116
.
Then, as shown in
FIG. 5
, in the formation of a barrier metal film
120
, a titanium/titanium nitride (Ti/TiN) film is formed on the contact hole
116
as a barrier metal film
120
before forming a tungsten film. The Ti film
120
a
is formed using a conventional sputtering method. The TiN film
120
b
is formed using a conventional sputtering or a Chemical Vapour Deposition (CVD) method, and is not limited to either one or the other method. The barrier metal film
120
reduces the contact resistance of the tungsten film, and improves the adhesiveness of the oxide film
114
and the tungsten film. In addition, during a later process for removing the tungsten film, the barrier metal film
120
is used as stopper layer. At this time, the barrier metal layer
120
can be formed on the align mark
118
.
Then, as shown in
FIG. 6
, in the formation of tungsten film
122
, a tungsten film
122
is formed on the oxide film
114
having a certain thickness burying the contact hole
116
. At this time, the tungsten film
122
is formed inside the align mark
118
. Since the align mark
118
has a bigger diameter than that of the contact hole
116
of the cell part, the align mark
118
is not buried with the tungsten film
122
, but has its bottom and sidewalls covered.
Then, as shown in
FIG. 7
, in the removal of the tungsten film
122
, the semiconductor substrate

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