Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-27
2001-08-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S672000, C438S682000
Reexamination Certificate
active
06271075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device which can reduce a manufacturing cost without dropping a performance of a logic-mixed-DRAM.
2. Description of the Related Art
A logic-mixed-DRAM (logic in DRAM) semiconductor device is a device essential to making a performance of a system higher. Especially, a performance of a logic section of the logic-mixed-DRAM semiconductor device is an element having influence on the performance of the system. So, it is important to maintain the logic section in a high performance.
In the logic-mixed-DRAM semiconductor device, in order to maintain the performance of the logic section, it is necessary to form a silicide layer in a part of a diffusion layer of the logic section to thereby drop a contact resistance. On the other hand, in a DRAM section of the logic-mixed-DRAM semiconductor device, it is not necessary to form a silicide layer in a part of a diffusion layer of the DRAM section.
For this reason, conventionally, silicide block PR (photo resist) (not shown) is formed in the DRAM section so that the silicide layer is not formed in the diffusion layer of the DRAM section and the silicide layer is formed in the diffusion layer of the logic section, after the formation of a gate polysilicon layer.
As mentioned above, although the logic-mixed-DRAM semiconductor device is valuable to making the performance of the system higher, it is impossible to avoid the increase of a manufacturing cost resulting from the mixture of the DRAM and the logic. Thus, it is desirable to reduce the cost without dropping the performance of the system.
Japanese Laid Open Patent Application (JP-A-Heisei 3-8339) discloses the following method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device in which a wiring and a p-type impurity region formed on a semiconductor substrate are connected is characterized in that the method comprises: a step of selectively removing an insulating film formed on the semiconductor substrate and then forming a contact region; a step of forming a wiring layer, in which a high temperature melting point metallic silicon compound layer is laminated on a polysilicon layer, on the semiconductor substrate so as to cover the contact region; a step of patterning the wiring layer; and a step of selectively removing the high temperature melting point metallic silicon compound layer on the contact region.
Japanese Examined Patent Application (JP-B-Heisei 4-590) discloses the following method of manufacturing a bipolar type of semiconductor device. The method is characterized in that it comprises: a step of forming a lamination film pattern of a metallic silicide film and a non-mono-crystal silicon film on a part of a first conductive type of semiconductor layer; a step of doping this lamination film pattern with a second conductive type of impurity layer; a step of etching and removing only the metallic silicide film by using an etching method having a selection for metallic silicide, in a portion of the lamination film pattern, and accordingly exposing the non-mono-crystal silicon film in the portion; a step of oxidizing the exposed portion of this non-mono-crystal silicon film and thereby forming a fetching electrode; a step of diffusing the impurity from the fetching electrode into the first conductive type of semiconductor layer through a heat treatment, and thereby forming a second conductive type of high concentration impurity region; a step of selectively doping the first conductive type of semiconductor layer from an oxide region of the non-mono-crystal silicon film with a second conductive type of impurity, and thereby forming a second conductive type of low concentration impurity region adjacent to the second conductive type of high concentration impurity region; a step of leaving an insulating film in a side wall of the fetching electrode by performing an anisotropy etching on an insulating film after deposition of an insulating film to cover the fetching electrode; and a step of forming a first conductive of high concentration impurity region in the second conductive type of low concentration impurity region.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problems of the conventional a method of manufacturing a semiconductor device. An object of the present invention is to provide a method of manufacturing a semiconductor device, which can reduce a cost without dropping a performance of the device. Another object of the present invention is to provide a method of manufacturing a semiconductor device having a logic section and a DRAM section, which can reduce a cost without dropping a performance of the device.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor device, includes (a) providing a DRAM section and a logic section in a substrate, (b) forming a first silicide layer in the DRAM section and a second silicide layer in the logic section, and (c) removing the first silicide layer.
In this case, a method of manufacturing a semiconductor device, further includes (d) forming a gate layer on the DRAM section, and (e) forming a side wall in a side portion of the gate layer, and wherein the (c) step is performed after the (e) step is performed such that the first silicide layer is removed in self alignment process.
In this case, the (c) step includes performing ion implantation on the first silicide layer.
Also in this case, the ion implantation is performed to change the first silicide layer to amorphous.
Further in this case, the (c) step includes removing the first silicide layer changed to amorphous by wet etching.
In this case, when the implanted ion is arsenic, the ion implantation is performed in a condition that an implantation energy of the ion is 20 to 50 KeV and a dose amount is 1×10
14
to 1 ×10
15
.
Also in this case, when the implanted ion is phosphorus, the ion implantation is performed in a condition that an implantation energy of the ion is 20 to 50 KeV and a dose amount is 1×10
14
to 5×10
15
.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device, includes (f) providing a DRAM section and a logic section in a substrate, (g) forming a first diffusion layer in the DRAM section and a second diffusion layer in the logic section, (h) forming a first silicide layer in the first diffusion layer and a second silicide layer in the second diffusion layer, (i) removing the first silicide layer to expose the first diffusion layer, and (j) forming a contact plug such that the contact plug is connected to the exposed first diffusion layer directly.
In this case, the (i) step includes removing the first silicide layer such that the first silicide layer corresponding to a lower portion of the contact plug is removed in self alignment process.
Also in this case, the (h) step includes forming the first silicide layer in the first diffusion layer, without using a silicide block masking the first diffusion layer not to form a silicide layer in the first diffusion layer.
Further in this case, a method of manufacturing a semiconductor device, further includes (k) forming an interlayer insulating layer on the first silicide layer, (l) forming a contact hole in a portion corresponding to the contact plug, of the interlayer insulating layer, and (m) forming a side wall on an inner surface of the contact hole to form a second contact hole, and wherein the (i) step includes removing the first silicide layer exposed through the second contact hole in self alignment process.
In this case, the (j) step includes forming the contact plug in the second contact hole.
Also in this case, the (i) step includes removing the first silicide layer by wet etching such that the side wall is not removed by the wet etching.
Further in this case, the wet etching is p
NEC Corporation
Tsai Jey
Young & Thompson
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