Method of manufacturing semiconductor device including a...

Details Method of manufacturing semiconductor device including a... Method of manufacturing semiconductor device including a...

2001-02-05

2003-07-29

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S683000

Reexamination Certificate

active

06599795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and to a semiconductor device manufactured thereby, and more particularly, to a technique for forming a silicide layer.
2. Description of the Background Art
Hybrid semiconductor device (system LSI) integrating DRAM and logic circuit so-called embedded DRAM (hereinafter called “eRAM”) has been manufactured for some time. In the eRAM, it is customary to form a silicide layer, for example, composed of CoSi
2
in upper layer portion of a diffusion layer of the logic circuit. The silicide layer is provided to reduce the parasitic resistance and parasitic capacity in the diffusion layer of the logic circuit and to enhance the speed of circuit operation.
In the following, the conventional method of manufacturing a semiconductor device with a step of forming the silicide layer will be described.
FIGS. 2A
to
2
H are cross-sectional views for describing a conventional method of manufacturing a semiconductor device.
With reference to
FIG. 2A
, a gate oxide film
2
is formed on a semiconductor substrate
1
having unillustrated active regions and isolation regions formed thereon beforehand. Next, gate electrodes
3
are formed on the gate oxide film
2
.
Here, the semiconductor substrate
1
comprises two kinds of regions: a region
11
(hereinafter called “DRAM circuit region”) where DRAM circuits are formed, and a region
12
(hereinafter called “logic circuit region”) where logic circuits are formed. The logic circuit region
12
may be a region where peripheral circuits of the DRAM circuit
11
are formed.
The gate electrodes
3
are formed by depositing a polycrystalline silicon film (hereinafter called “polysilicon film”)
31
, a tungsten silicide film
32
, and a TEOS oxide film
33
in this sequence.
Next, as shown in
FIG. 2B
, the both sides of the gate electrodes
3
are oxidized by a few nanometers (corresponding to an oxide film
34
in FIG.
2
B). Next, a first insulating film
4
, for example a silicon nitride film, is formed all over the semiconductor substrate
1
by LPCVD (low pressure chemical vapor deposition) method.
Next, although not shown, a resist pattern is formed on the first insulating film
4
. Further, the first insulating film
4
is removed except at the top and at the both sides of the gate electrodes
3
in the logic circuit region
12
by dry etching with the resist pattern used as a mask.
Thus, a sidewall insulating film
41
, which is made of the first insulating film
4
, is formed on the top and the both sides of the gate electrodes
3
in the logic circuit region
12
, as shown in FIG.
2
C.
Next, ions of impurities are implanted into the semiconductor substrate
1
with the first insulating film
4
and the sidewall insulating film
41
used as a mask.
Thus, source/drain regions
5
, which are served as n
+
-type (or p
+
-type) diffusion layer, are formed in the semiconductor substrate
1
of the logic circuit region
12
(see FIG.
2
C).
Next, a silicide layer is formed as follows.
With reference to
FIG. 2D
, a protection film
6
serving as silicide protection film, for example a TEOS oxide film, is formed all over the semiconductor substrate
1
by LPCVD method.
Next, although not shown, a resist pattern is formed on the protection film
6
. Further, the protection film
6
, is subjected to dry etching with the resist pattern used as a mask.
Thus, the protection film
6
is formed on the logic circuit region
12
except for certain gate electrodes
3
a
and except for specific regions
51
of the diffusion layer
5
around the certain gate electrodes
3
a
, as shown in FIG.
2
D. Namely, the protection film, which is formed on the first insulating film
4
in the DRAM circuit region
11
and formed on the specific regions
51
and the certain gate electrodes
3
a
in the logic circuit region
12
, is removed by dry etching.
Here, when the protection film
6
is removed from the DRAM circuit region
11
, the first insulating film
4
formed in the preceding process still exists. Therefore, the first insulating film
4
is served as the silicide protection film, no silicide layer is formed on the semiconductor substrate
1
in the DRAM circuit region
11
.
Next, as shown in
FIG. 2E
, a silicide layer
7
, for example CoSi
2
, is formed in an upper layer portion of the specific regions
51
of the diffusion layer
5
in the logic circuit region
12
by a known self-aligned silicide technique (hereinafter called “salicide technique”).
Thus, the silicide layer
7
is formed in the diffusion layer
5
of the logic circuit region
12
.
Next, as shown in
FIG. 2G
, openings
42
and
61
, which are used as contacts (which will be described in detail later), are formed respectively in the first insulating film
4
of the DRAM circuit region
11
and in the protection film
6
of the logic circuit region
12
by photolithography and by dry etching. Next, an interlayer dielectric
8
, for example a silicon oxide film, is formed by CVD method all over the semiconductor substrate
1
so as to cover all of the gate electrodes
3
.
Next, although not shown, a resist pattern is formed on the interlayer dielectric
8
.
Subsequently, as shown in
FIG. 2H
, contact holes
82
,
83
and
84
are formed in the interlayer dielectric
8
by dry etching with the resist pattern as a mask. Here, the contact holes
82
extend from a surface
81
of the interlayer dielectric
8
to the semiconductor substrate
1
through the openings
42
. The contact holes
83
extend from the surface
81
to the conductive layer
7
. The contact holes
84
extend from the surface
81
to the diffusion layer
5
through the openings
61
.
Finally, although not shown, capacitors and wirings are formed. Thus, a hybrid semiconductor device having DRAM circuits with logic circuits is manufactured.
However, in the conventional method, there are problems as follows.
In the conventional method, as shown
FIG. 2F
, massive residues
71
are remained on the surface of the protection film
6
and the first insulating film
4
after the formation of the silicide layer
7
. In particular, as shown in
FIG. 2F
, the massive residues
71
are remained between the gate electrode gaps
36
in memory cells of the DRAM circuit region
11
. Here, the gate electrode gap
36
is on the first insulating film
4
between the gate electrodes
3
.
To the inventors' knowledge, no prior art has dealt with the massive residues
71
so far.
Under TRXRF (total reflection of X-ray fluorescence analysis method), the inventors confirmed, the massive residues
71
contain metal cobalt (Co) on the order of 10
11
to 10
12
atoms/cm
2
.
The probable cause of the remains of the massive residues
71
will be described as follows. The amount of massive residues
71
is directly proportional to the amount of the substance removed by sputter etching. The sputter etching process is performed prior to formation of the silicide layer
7
in order to remove a naturally formed oxide film from the silicon surface of the semiconductor substrate (silicon substrate)
1
. Silicon-rich portions are formed, for example, on the first insulating film
4
between the gate electrodes
3
(gate electrode gaps
36
) in the DRAM circuit region
11
by the sputter etching process. These portions presumably turn into the massive residues
7
, and the residues
7
are remained.
The massive residues
71
thus formed can become a major cause of metal contamination.
The massive residues
71
, which are remained in such narrow spaces as the gate electrode gaps
36
in the DRAM circuit region
11
, can cause short-circuits between contact plugs of adjacent bit lines. Such short-circuits result in faulty bits.
As shown in
FIG. 2G
, the massive residues
71
are not removed during formation of the contact openings
42
by dry etching. Therefore, although not shown, column-like residues could be formed in the openings
42
with the massive residues
71
acting as a mask.
Accordingly, the remains of the

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