Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-25
2003-12-02
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C438S529000
Reexamination Certificate
active
06656800
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-191589, filed Jun. 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method for facilitating precise and stable forming and holding of a impurity profile that exists at a channel portion under a transistor gate electrode, which is essential to reduce a transistor gate length to the minimum in a technique (hereinafter, referred to as a gate prefabrication technique) for forming an element isolation region in a self alignment manner by using a transistor forming region that has been formed in advance in order to make it possible to form transistors with high concentration. This manufacturing method is applied to manufacture of peripheral transistors of an NAND-type flash memory manufactured by employing a gate prefabrication technique, for example.
2. Description of the Related Art
There has been made an attempt to form a MOS type semiconductor device, in which a part of a multilayered gate electrode, for example, a first layer is first formed in a predetermined region for forming an impurity diffusion layer and a channel portion. Then, an element isolation region is formed in a self alignment manner by employing the first layer as a mask, thereby achieving high concentration and low cost (refer to T. Ukeda et al., SSDM 1996, pp. 260-262). A description will be given with reference to
FIG. 12A
to
FIG. 12D
by way of showing this conventional attempt. First, a N-Well
103
and P-Well
102
are formed on a P-type silicon substrate
101
, and a SiO
2
film
104
is formed on the P type silicon substrate
101
. Further, using a resist pattern (not shown) as a mask converting the P-Well
102
, a boron “B” ion
105
is implanted onto the N-Well
103
in order to perform P type transistor channel control. Furthermore, with the resist pattern
106
being employed as a mask, a “B” ion
107
is implanted on the P-Well
102
in order to perform N type transistor channel control.
Next, after removing the SiO
2
film
104
, a gate oxide film
108
is formed by thermal oxidization, and a polysilicon film
109
is formed (FIG.
12
B). At this time, the boron “B” ions implanted for the purpose of transistor channel control shown in
FIG. 12A
are activated, and diffuses into the P type silicon substrate
101
as impurity diffusion regions
105
′ and
107
′, respectively, as shown in FIG.
12
B.
Next, the polysilicon film
109
that exists in a desired element isolation region is etched off; and the SiO
2
film
108
and P type silicon substrate
101
are etched off to form a trench
110
T. The SiO
2
film
110
is buried in the thus formed trench
110
T by a CVD technique, as shown in
FIG. 12C
, and then, heat treatment is applied to the buried film. The heat treated film is flattened using a CMP method, and the silicon oxide film remaining on the polysilicon film
109
is etched away.
Next, a polysilicon film
111
is formed on the SiO
2
film
110
buried in the trench
110
T and on the polysilicon film
109
, and then, a resist pattern
112
is formed on a predetermined region of the polysilicon film
111
for forming a gate electrode wiring layer. At this time, it is well known that a high temperature densifying step is required because there is a need to increase concentration of the SiO
2
film
110
in order to function the film
110
buried in the trench
110
T as an insulation film for element isolation. The SiO
2
film
110
is not a thermal oxide film, but a sintered CDV film.
With this heating step, the boron “B” impurities introduced into the silicon substrate
101
for the purpose of transistor channel control further diffuses deeply into the silicon substrate
101
, and impurity diffusion regions
105
″ and
107
″ are formed, respectively, as shown in FIG.
12
C.
Next, using the resist pattern
112
as a mask, the patterns of the polysilicon film
111
and polysilicon film
109
are formed by an etching process. Then, after releasing the resist pattern
112
, a step of forming an LDD region
113
, a step of forming a side wall
114
of a gate electrode, and a step of forming a diffusion layer
116
are carried out. Further, an N type transistor and a P type transistor are formed through a post-oxidization step at 800° C. and for about 600 minutes. Of course, at this heating step as well, the impurity of boron “B” slightly introduced into the silicon substrate
101
diffuses over the wide area of the silicon substrate
101
.
A semiconductor device manufactured in accordance with the above described steps is formed in a self alignment manner together with the channel portion and diffusion layer area that configure transistors. Thus, an element isolation region can be formed to have a minimum size. Therefore, this technique can be essential in forming a transistor with high concentration.
In contrast, there occurs a disadvantage that a channel length of a transistor cannot be reduced to the minimum for the reasons described below. Of course, it is required to reduce the channel length to the minimum in order to miniaturize a transistor and provide a high element concentration. In order to reduce the channel length to the minimum, it is essential to control the transistor channel profile. For example, in general, in an buried channel P type transistor which is widely used, as is well known, it is effective to set this buried channel closer to the silicon substrate surface. However, it is necessary to provide a sharp impurity profile in order to achieve this channel positioning. In addition, in an NMOS as well, it is well known that a better controlled profile is effective.
Hence, in the conventional example shown in
FIG. 12A
to
FIG. 12D
, an element isolation region is manufactured in a self alignment manner with respect to a transistor forming region, and thus, the element isolation region can be finely manufactured. However, from the reasons described previously, with respect to a transistor channel length, it is very difficult to realize it due to the difficulty of the channel impurity profile control. Thus, there is a disadvantage that the transistor channel length cannot be reduced to the minimum, and the transistor forming region occupies a large area on a chip. Hereinafter, the reasons will be described in detail.
Conventional semiconductor device manufacturing steps widely employed include the steps of: providing an element isolation insulation film on the surface of a substrate; introducing impurities for the purpose of transistor channel control; forming a gate insulation film; and forming a gate electrode of a transistor.
In contrast, the prior art process steps shown in
FIG. 12A
to
FIG. 12D
include the steps of: introducing impurities for the purpose of transistor channel control; forming a gate insulation film; forming a part of a gate electrode; and forming an element isolation insulation film. Thus, the heating step after introducing impurities for the purpose of transistor channel control additionally is included in the step of forming an element isolation insulation film. This heating step is carried out at 850° C. and for about 30 minutes, for example. With this heating step, impurities added for the purpose of transistor channel control diffuse unnecessarily and significantly into the substrate, which makes it difficult to perform precise channel profile control. This leads to impairment of reducing the transistor channel length to the minimum.
In addition, if the transistor channel profile cannot be controlled as a desired steep profile, it is known that the following failure will occur in addition to the impairment of reducing the transistor channel length to the minimum. For example, in the case where “B (boron)” added for the channel control is further diffused as P type impurities in an N type transistor forming region, t
Kabushiki Kaisha Toshiba
Perkins Pamela
Zarabian Amir
LandOfFree
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