Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-17
2002-03-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000
Reexamination Certificate
active
06352891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability.
2. Description of the Related Art
In recent years, a merged DRAM (Dynamic Random Access Memory)—logic LSI has been used in many cases. In the merged DRAM-logic LSI, a logic integrated circuit and a DRAM are simultaneously formed on a single chip, to make a performance of a ULSI (Ultra Large Scale Integration) higher and make a function thereof higher. This merged DRAM-logic LSI is expected to include a large capacity of DRAM without drop of the performance of logic parts. It is also expected that the merged DRASM-logic LSI can be manufactured at a low cost.
For this reason, the structure in which silicide layer is formed on the surface of high impurity concentration diffusion layer serving as a source/drain of a MOSFET is used to achieve the high performance, in the merged DRAM-logic LSI. Silicon nitride film is often used as a spacer for covering a side portion of a gate electrode to form this silicide layer in self-alignment,
On one hand, in a general purpose DRAM, the silicide layer is not formed on the surface of the diffusion layer, in view of a cost. On the contrary, if the DRAM is merged with the logic LSI, the silicide layer can be formed on the surface of the diffusion layer of the MOSFET (Metal Oxide Silicon Field Effect Transistor) of the DRAM without increasing the cost.
However, the diffusion layer used as the source/drain of the MOSFET in a DRAM memory cell is the diffusion layer having a low impurity concentration of which a junction depth is shallow. Here, the reason why the source/drain of the MOSFET in the DRAM memory cell is formed as the diffusion layer having the low impurity concentration of which the junction depth is shallow is to suppress a short channel effect, suppress a junction leak current and improve a hot carrier resistance. Moreover, silicon oxide film is used as an insulating film spacer formed on the side portion of the gate electrode of the MOSFET.
However, the following first to third problems are incurred if the silicide layer is formed on the surface of the diffusion layer having the low impurity concentration of which the junction depth is shallow as the source/drain of the MOSFET in the DRAM memory cell.
Firstly, a contact resistance is high between the silicide layer and the diffusion layer having the low impurity concentration. Although the silicide layer is formed on the region of the source/drain, there may be a case in which an external resistance in the region of the source/drain is high, conversely to the original object.
Secondly, the shallow depth of the diffusion layer of the source/drain causes the junction leak current to be increased. Thirdly, the use of the silicon nitride film as the insulating film spacer on the side portion of the gate electrode causes the hot carrier resistance to be deteriorated.
A method of selectively forming a silicide layer on a diffusion layer in a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-205865), as a method of avoiding a part of the above-mentioned problems. The gazette discloses a method that a silicide layer is formed on a surface of the diffusion layer in a first MOSFET of a semiconductor device and a silicide layer is not formed on a surface of the diffusion layer in a second MOSFET of the semiconductor device.
The conventional example noted in the gazette will be described below with reference to
FIGS. 1
to
5
.
At first, an N-type well
102
, a field oxide film
103
, a gate oxide film
104
, a gate electrode
105
formed of polysilicon and the like, a P-type low impurity concentration region
107
and side walls
106
are formed on the surface of a semiconductor substrate
101
, in FIG.
1
.
Next, as shown in
FIG. 2
, a silicon nitride film
112
serving as a first insulating film is grown on an entire portion of the surface. The silicon nitride film
112
has a function of a mask to divide the source/drain between the region on which a silicide layer is formed and the region on which a silicide layer is not formed. The silicon nitride film
112
has a thickness of, for example, about 30 nm. Then, a silicon oxide film
113
serving as a second insulating film is deposited on the entire portion of the surface in a thickness of about 100 nm.
Next, as shown in
FIG. 3
, photolithography technique is used to etch the silicon oxide film
113
corresponding to the region on which the silicide layer is formed. After that, the silicon nitride film
112
corresponding to the same region is etched.
Next, as shown in
FIG. 4
, a metal having a high melting point, for example, Ti is sputtered on the entire surface in about 80 nm. Then, annealing is performed thereon so that Ti and Si react to together in the region, in which the silicon oxide film
113
is removed, to accordingly form a Ti silicide
109
. The Ti silicide
109
has a thickness of, for example, about 100 nm.
Next, as shown in
FIG. 5
, the Ti that is not constitutes the Ti silicide
109
and is present on the region where the silicon oxide film
113
is not removed, is removed by the etching. Then, a silicon oxide film
114
with a thickness of about 25 nm is formed on the entire surface. After that, a P-type high concentration impurity region
111
a
is formed by, for example, ion implantation of boron.
However, in the conventional example, it is necessary to increase a lithography process to form the region where the Ti silicide
109
is formed and the region where it is not formed. Thus, the conventional example has the defect of increasing the manufacturing process.
Moreover, in the conventional example, the same material is used in the region where the silicide layer is formed and the region where it is not formed, for the side wall of the gate electrode of the MOSFET. Thus, the simple application of the conventional example to the merged DRAM-logic device results in the problem that the hot carrier resistance of the MOSFET is deteriorated.
To change the material of the side wall in the region where the Ti silicide,
109
, is formed, the once-formed side wall
106
is removed by using the lithography process. After that, a next side wall
106
can be formed newly. However, in order to carry out this treatment, it is necessary to increase one or more lithography processes. Thus, this has the defect of increasing the manufacturing process.
Japanese Laid Open Patent Application (JP-A-Heisei 9-116113) discloses a method of manufacturing a semiconductor device, as described below. A memory cell is formed after a circuit field effect transistor is covered with insulating film. After the formation of the memory cell, the surface of diffusion layer of the circuit field effect transistor is exposed to then form the covered conductive layer on the exposed surface of the diffusion layer.
Japanese Laid Open Patent Application (JP-A-Heisei 4-262573) discloses a method of manufacturing a semiconductor device, as described below. A first side wall protection film that is common to a memory cell array formation region and a peripheral circuit formation region is formed when forming a transistor having LDD structure. After that, anisotropy etching is further performed on only the first side wall protection film in the peripheral circuit formation region to thereby form a second side wall protection film having a width narrower than that of the first side wall protection film. Then, LDD regions having different widths are formed in the respective memory cell array region and peripheral circuit region, with these first and second side wall protection films as respective masks.
Japanese Laid Open Patent Application (JP-A-Heisei 10-41480) discloses a method of manufacturing a semiconductor memory device, as described below. A cell array region, a core region and a peripheral circuit region are respectively formed in a semiconductor memory device having transistor
Kennedy Jennifer M.
Niebling John F.
Scully Scott Murphy & Presser
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