Method of manufacturing semiconductor device having thin...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S161000

Reexamination Certificate

active

07029957

ABSTRACT:
A method of manufacturing a semiconductor device includes the steps of, (1) preparing an SOI substrate, (2) forming a metal layer on the SOI substrate, (3) performing a first anneal treatment to the metal layer at a relatively low temperature in order to transform the metal layer to a first silicide layer, (4) forming an insulating layer on the first silicide layer, and (5) forming a contact hole, which reaches the first silicide layer, in the insulating layer; and (6) performing a second anneal treatment to the silicide layer at a relatively high temperature in order to transform the first silicide layer to a second silicide layer.

REFERENCES:
patent: 6331486 (2001-12-01), Cabral et al.
patent: 6624010 (2003-09-01), Ikegami
patent: 6664598 (2003-12-01), Dennard et al.
patent: 6800513 (2004-10-01), Horiuchi et al.
“Deep Sub-0.1 μm MOSFET's with very thin SOI layer for ultra-low power consumption”, C-II vol. J81-C-II No. 3, pp 313-319 published in Mar., 1998 by The Institute of Electronics, Information and Communication Engineers Author: Makoto Takamiya, Yuri Yasuda and Toshiro Hiramoto Note: English Summary is attached.
“Optimization of Series Resistance in Sub-0.2 mm SOI MOSFET's”, IEEE Electron device letters, vol. 15, No. 09 p. 363 published in Sep., 1994 Author: Lisa T. Su, Melanie J. Sherony, Hang Hu, James E. Chung and Dimitri A. Antonidis.

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