Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2003-04-10
2004-02-17
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S763000, C438S778000, C438S931000
Reexamination Certificate
active
06693046
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on Japanese Patent Applications No. 2002-338294, filed on Nov. 21, 2002, and No. 2002-187802, filed on Jun. 27, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly to a method of manufacturing a semiconductor device having multilevel wiring layers.
B) Description of the Related Art
The integration degree and operation speed of large scale integrated circuits have been improved increasingly. As the integration degree is improved, semiconductor elements such as transistors constituting an, integrated circuit are becoming smaller and the operation speed of smaller semiconductor elements is also improved.
As the micro patterning and integration degree of semiconductor elements are improved, wiring in a large scale integrated circuit becomes fine and multileveled. A transmission speed of a signal in a wiring line is determined almost by a wiring resistance and a wiring parasitic capacitance.
Reduction in a wiring resistance can be realized by changing the main component of a wiring from aluminum (Al) to copper (Cu) having a lower resistivity. Making the resistance of wiring material lower than that of Cu is practically difficult. As Cu is used as the material of a wiring, it becomes necessary to prevent diffusion of Cu in the wiring into an interlayer insulating film. SiN, SiC or SiCO is mainly used as the material of a copper diffusion preventive layer. The copper diffusion preventive layer has generally a high water repellency.
If the distance between wiring lines becomes short because of high integration of semiconductor devices, the parasitic capacitance between wiring lines increases assuming that the wiring thickness is the same. If the parasitic capacitance is lowered by thinning the wiring thickness, the wiring resistance increases. In order to lower the wiring capacitance, it is most effective to use material having a low dielectric constant, so-called low k material.
In this specification, the value of dielectric constant will be referred to by the specific dielectric constant.
There are many reports on a method of forming an interlayer insulating film by using material having a dielectric constant lower than that of silicon oxide in order to realize a high speed operation of a semiconductor device. Since a wiring capacitance becomes serious particularly for lower level micro patterned wiring layers, it has been studied to form an interlayer insulating film by using a low dielectric constant material.
If a low dielectric constant insulating material layer is formed in a liquid phase on a copper diffusion preventive layer having a hydrophobic surface, adhesion is likely to be lowered. If a low dielectric constant insulating material layer is formed on a copper diffusion preventive layer, by a coating method in particular, adhesion is likely to be lowered. In the multilevel wiring structure, peel-off at the interface between a low dielectric constant insulating layer and a hydrophobic underlying layer may occur. As the number of wiring layers increases, peel-off of a low dielectric constant insulating layer becomes more conspicuous.
SUMMARY OF THE INVENTION
An object of this invention is to provide a method of manufacturing a semiconductor device capable of suppressing peel-off of a low dielectric constant insulating layer from a hydrophobic underlying layer.
Another object of the invention is to provide a method of manufacturing a semiconductor device of a high performance, a high reliability and a high integration.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of said first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than a specific dielectric constant of silicon oxide on said first hydrophobic insulating layer having a hydrophilized surface.
With this method, adhesion of a multilevel wiring structure can be improved and peel-off can be suppressed.
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patent: 6476988 (2002-11-01), Yudasaka
patent: 2001-345317 (2001-12-01), None
patent: 2002-315900 (2002-10-01), None
Fukuyama Shun-ichi
Takigawa Yukio
Fujitsu Limited
Picardat Kevin M.
Westerman Hattori Daniels & Adrian LLP
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