Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-03
2004-11-23
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S299000
Reexamination Certificate
active
06821856
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and its fabrication method, particularly to a MIS transistor whose integration degree is improved and its fabrication method.
Because a device has been further fined in recent years, it has been necessary to reduce parasitic capacitance between body region and source and drain regions in order to improve the operation speed of a MIS transistor. Further, it is also a subject to decrease the cell area and realize high integration of a semiconductor device.
FIGS. 11A and 11B
are a top view and a sectional view of a conventional MOS transistor.
As shown in
FIGS. 11A and 11B
, the conventional MOS transistor includes an Si substrate
101
containing p-type impurities, an isolation insulating film
102
formed on the p-type Si substrate
101
, a gate-insulating film
105
made of silicon oxide (SiO
2
) formed on the Si substrate
101
, a gate electrode
103
made of polysilicon containing n-type impurities formed on the gate-insulating film
105
, a sidewall
106
formed on the side face of the gate electrode, source and drain regions
104
a
and
104
b
formed in regions located at the both sides of the gate electrode in the Si substrate
101
and respectively containing n-type impurities, a gate silicide film
107
formed on the gate electrode
103
, a silicide film
108
formed on the source and drain regions
104
a
and
104
b
respectively, a layer-insulating film
110
formed on the substrate, and a plug
109
passing through the layer-insulating film
110
and reaching the silicide film
108
on the source and drain regions
104
a
and
104
b.
Though the transistor is a general n-channel MOS transistor, the structure is the same as that of a p-channel MOS transistor.
In the case of a conventional MOS transistor, the cell area is decreased by mainly decreasing the gate length.
However, in the case of the conventional MOS transistor shown in
FIGS. 11A and 11B
, it is difficult to greatly decrease the device area because it is necessary to develop a new fabrication technology for realizing microfabrication and the device area can hardly be decreased because the transistor is already microfabricated.
However, an example of realizing a high-speed operation by improving the MOS transistor, decreasing the area of an active region, and reducing a parasitic capacitance is reported (H. Kotaki et al., “Novel Low Capacitance Sidewall Elevated Drain Dynamic Threshold MOSFET (LCSED) for Ultra Low Power Dual Gate CMOS Technology”, IEDM98 Ext. Abst. p. 415).
In the case of the above example, a stacked source-drain structure is used in order to reduce an active region. Thereby, the area of the active region is reduced and it is possible to decrease a parasitic capacitance.
However, in the case of the above example, though the area of the active region and the parasitic capacitance are decreased, a trouble occurs that the parasitic capacitance cannot be completely reduced because a new extra capacitance is generated on a gate electrode and between the stacked source and drain. Moreover, a trouble occurs that the fabrication process becomes complex.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device in which areas of an active region and a cell are reduced and a high-speed operation and a high integration can be realized and its fabrication method.
A semiconductor device of the present invention comprises a semiconductor substrate having an active region; an isolation insulating film formed on the semiconductor substrate to surround the active region; a semiconductor layer formed over the active region and part of the isolation insulating film; a gate-insulating film formed on part of the semiconductor layer which is located on the active region; a gate electrode made of a conductive film formed on the gate-insulating film; and source and drain regions formed in parts of the semiconductor layer which are located closer to both sides of the gate electrode; wherein at least parts of the semiconductor layer which is located over the isolation insulating film serves as the source and drain regions.
Thereby, because source and drain regions are also formed on the isolation insulating film, it is possible to decrease the area of the active region and the cell area and resultantly further increase the integration degree of a device than ever. Moreover, because a source-body junction area and drain-body junction area can be decreased, it is possible to reduce a parasitic capacitance. Therefore, the parasitic capacitance is not increased compared to the case of a conventional semiconductor device even if the impurity concentration in a substrate is raised.
When the semiconductor layer is a single-crystal layer on the active region and a polycrystalline layer over the isolation insulating film, the semiconductor layer on the active region can show a superior electrical characteristic as a channel and the semiconductor layer above the isolation insulating film can show a superior electrical characteristic as source and drain regions having a small electric resistance.
When the semiconductor device of the present invention further comprises a wiring connected to the source and drain regions and at least a part of the contact region between the wiring and the source and drain regions is formed above the isolation insulating film, it is possible to greatly decrease a cell area compared to the case of a conventional semiconductor device having a contact region above an active region.
Moreover, in a region of the semiconductor layer located on the isolation insulating film, a base semiconductor layer is formed between the semiconductor layer and the isolation insulating film. Thereby, it is possible to securely form a semiconductor layer above the isolation insulating film.
Furthermore, part of the semiconductor layer which is located over part of the isolation insulating film may have a greater thickness than part of the semiconductor layer which is located on the active region.
When the semiconductor substrate and the semiconductor layer are both made of silicon, it is possible to use the conventional fabrication equipment of a MOS transistor and therefore, easily fabricate a device and reduce the fabrication cost.
When the semiconductor layer contains at least either of germanium and carbon and thereby, the carrier mobility in the crystals such as SiGe and SiGeC is higher than the case of individual Si, it is possible to accelerate the operation speed of a device by using these crystals as channel layers. Moreover, SiGe and SiGeC respectively have a smaller band gap than that of individual Si, it is possible to lower a threshold voltage.
When the semiconductor substrate has an SOI structure and thereby, the parasitic capacitance between wirings is reduced, it is possible to further accelerate the operation speed of a device.
When the gate electrode is electrically connected with the body region in the semiconductor substrate located immediately below the gate electrode, it is possible to lower a threshold voltage when a gate bias is on. Moreover, because a longitudinal electric field on the surface of the substrate is small, it is possible to prevent deterioration of mobility due to increase of the longitudinal electric field and increase a driving force.
A first fabrication method of a semiconductor device of the present invention comprises a step (a) of forming an isolation insulating film for surrounding an active region in a semiconductor substrate having the active region, a step (b) of growing a semiconductor layer over the active region and a part of the isolation insulating film, a step (c) of forming a gate-insulating film and a gate electrode in the region located on the semiconductor layer on the active layer, and a step (d) of performing implantation of impurity ions and forming source and drain regions in parts of the semiconductor layer which are located closer to both sides of the gate electrode formed in the step (c).
According to the above method, it is p
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Nguyen Van Thu
Smith Brad
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