Method of manufacturing semiconductor device comprising high vol

Details Method of manufacturing semiconductor device comprising high vol Method of manufacturing semiconductor device comprising high vol

1999-08-26

2000-12-12

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438211, 438258, 438264, H01L 21336

Patent

active

061597996

ABSTRACT:
A method of manufacturing a semiconductor device includes the steps of preparing a substrate having a high-voltage applied region, a peripheral region, a cell region with at least first and second portions, the high-voltage applied region having a well formed therein; simultaneously forming a plurality of spaced floating gates on the first and second portions of the cell region and a plurality of spaced first gates on the high-voltage applied region; implanting first impurity ions in the high-voltage applied region of the substrate using the first gates as a mask to form a first impurity region, the floating gates masking the cell region from the first impurity ions; simultaneously forming control gates on the respective floating gates of the cell region and a plurality of spaced second gates on the peripheral region; selectively etching one of the control gates and one of the floating gates to form a plurality of gate patterns in the first portion of the cell region; and implanting second impurity ions in the substrate at sides of the gate patterns and at sides of the first gates to simultaneously form second impurity regions at sides of the gate patterns and twice implanted first impurity regions at sides of the first gates.

REFERENCES:
patent: 4471373 (1984-09-01), Shimizu et al.
patent: 4851361 (1989-07-01), Schumann et al.
patent: 5057448 (1991-10-01), Kuroda
patent: 5591658 (1997-01-01), Cacharelis
patent: 5917218 (1999-06-01), Choi et al.
Seiichi Mori et al., High Speed Sub-halfmicron Flash Memory Technology with Simple Stacked Gate Structure Cell, 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 53-54.

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