Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-21
2004-05-18
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S783000, C438S760000, C438S761000, C438S788000, C257S759000, C257S760000, C257S752000, C257S757000, C257S637000, C257S634000, C257S646000
Reexamination Certificate
active
06737319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a multi-layered wiring structure, and further to a semiconductor device manufactured by the above-mentioned method of manufacturing a semiconductor device.
2. Description of the Background Art
Regarding semiconductor integrated circuits, higher speed, higher performance, and miniaturization of devices are being promoted along with generations, and in particular, signal propagation delays constitute a critical problem in accordance with the miniaturization. The signal propagation delays are classified into gate delay components and wiring delay components. The gate delays tend to decrease in accordance with the miniaturization of transistors, whereas the wiring delays tend to increase in accordance with the miniaturization of the wirings. The wiring delays are determined by the product CR of wiring capacitance C and wiring resistance R. Therefore, reduction of the wiring capacitance C by lowering the electric permittivity of a wiring interlayer dielectric film is now being considered as a measure for restraining the wiring delays. One of such measures is directed to reduction of capacitance by use of a silicon oxide film containing fluorine (F-doped silicate glass, hereafter referred to as FSG film in this specification) as the wiring interlayer dielectric film.
FIGS. 9
to
13
are cross section views illustrating steps in a method of manufacturing a semiconductor device according to a background art. First, a plurality of wirings
102
a
to
102
e
are formed as a first wiring layer on an upper surface of an underlying dielectric film
101
(FIG.
9
). Next, an FSG film
103
is formed on the structure shown in
FIG. 9
(FIG.
10
). Then, a silicon oxide film
104
containing no fluorine (undoped silicate glass, hereafter referred to as USG film in this specification) is formed on the structure shown in
FIG. 10
(FIG.
11
). Next, the USG film
104
is polished and removed by a predetermined thickness from an upper surface thereof by the CMP method to flatten the surface of the USG film
104
. This completes an interlayer dielectric film
150
a
made of the FSG film
103
and a USG film
105
(FIG.
12
). Then, after the surface of the interlayer dielectric film
150
a
is cleaned with HF, a plurality of contact holes
106
a
to
106
e
, which are respectively in contact with the wirings
102
a
to
102
e
and each filled with a conductor plug, are formed in the interlayer dielectric film
150
a
. Then, after a metal film is formed over an entire surface of the interlayer dielectric film
150
a
, the metal film is patterned by the photolithography method and the anisotropic dry etching method to form a plurality of wirings
107
a
to
107
e
, which are respectively in contact with the contact holes
106
a
to
106
e
, as a second wiring layer (FIG.
13
).
However, from the viewpoint of reduction in the wiring capacitance, it is effective to increase the ratio occupied by the FSG film
103
in the interlayer dielectric film
150
a
by increasing the thickness of the FSG film
103
.
FIGS. 14
to
17
are cross section views showing steps in a method of manufacturing another semiconductor device according to a background art. First, on the structure shown in
FIG. 9
, an FSG film
108
is formed to a thickness larger than the thickness of the wirings
102
a
to
102
e
(FIG.
14
). Next, on the FSG film
108
, a USG film
109
is formed to a thickness larger than the thickness of the FSG film
108
(FIG.
15
). Then, the USG film
108
is polished and removed by a predetermined thickness from an upper surface thereof by the CMP method to flatten the surface of the USG film
104
to such an extent that the FSG film
108
is not exposed. This completes an interlayer dielectric film
150
b
made of the FSG film
108
and a USG film
110
(FIG.
16
). Then, after the surface of the interlayer dielectric film
150
b
is cleaned with HF, contact holes
106
a
to
106
e
and wirings
107
a
to
107
e
are formed in the same manner as described above (FIG.
17
).
However, according to the conventional method of manufacturing a semiconductor device shown in
FIGS. 14
to
17
, a part of the upper surface of the FSG film
108
will be exposed by the CMP process of the USG film
109
if variations occur in the thickness of the USG film
109
formed on the FSG film
108
or in the amount of the USG film
109
polished in the CMP step.
Therefore, in the subsequent cleaning step, a step difference is created on the upper surface of the interlayer dielectric film
150
b
due to the difference in the etching rate of HF between the FSG film and the USG film (for example, if a 1% diluted HF is used, the etching rate of the FSG film is 40 nm/min while the etching rate of the USG film is 20 nm/min).
FIG. 18
is a cross section view showing such a step difference. The upper surface of the FSG film
108
is at a level lower than the upper surface of the USG film
110
to form a step difference
11
at a boundary part.
If the wirings
107
a
to
107
e
are formed on the interlayer dielectric film
150
b
by the above-mentioned method under such a circumstance where the step difference
111
has been created, a metal side wall is formed along the step difference
111
.
FIGS. 19 and 20
are a cross section view and a top view showing such a side wall. A metal side wall
112
is formed along the step difference
111
. Referring to
FIG. 20
, a wiring
107
e
2
is formed in parallel with a wiring
107
e
1
in an FSG-exposed region where the upper surface of the FSG film
108
is exposed. The wiring
107
e
1
and the wiring
107
e
2
are electrically connected with each other via the metal side wall
112
. In other words, a short circuit occurs between the wirings in the upper layer, i.e. the second wiring layer.
Also, in the case where the wirings
107
a
to
107
e
are to be formed as buried wirings, that is, to be more specifically described, in the case where the steps of (a) depositing a dielectric film over an entire surface of the structure shown in
FIG. 18
, (b) removing the dielectric film to form a recess in a region where the wirings
107
a
to
107
e
are to be formed, (c) depositing a metal film over an entire surface to a thickness larger than the thickness that fills the recess, and (d) performing the CMP until the dielectric film is exposed, are performed in this order to form the wirings
107
a
to
107
e
buried in the recess, a part of the metal film remains on the dielectric film between the wiring
107
e
1
and the wiring
107
e
2
to generate a short circuit between the wiring
107
e
1
and the wiring
107
e
2
.
Thus, the conventional method of manufacturing a semiconductor device involves a problem such that, in the case where a part of the upper surface of the FSG film constituting the interlayer dielectric film is exposed due to variations in a production step, a step difference occurs on the upper surface of the interlayer dielectric film in a later cleaning step, leading to a short circuit between the wirings in the upper wiring layer.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of (a) forming a first layer wiring on an underlying layer; (b) forming a first dielectric film on a structure obtained by the step (a); (c) forming a second dielectric film on the first dielectric film, the second dielectric film being made of a different material from the first dielectric film; (d) reducing a thickness of the second dielectric film by a predetermined thickness from a surface thereof to form an interlayer dielectric film made of the first dielectric film and the second dielectric film having a reduced thickness; (e) cleaning the surface of the interlayer dielectric film with a cleaning liquid whose etching rate to the first dielectric film and etching rate to the second dielectric film are substantially
Goto Kinya
Matsuura Masazumi
Morimoto Noboru
Renesas Technology Corp.
Yevsikov V.
LandOfFree
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