Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1999-08-05

2000-05-23

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438304, 438305, 438301, 438299, 438306, H01L 21336

Patent

active

060665351

ABSTRACT:
A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

REFERENCES:
patent: 5266823 (1993-11-01), Noji et al.
patent: 5422505 (1995-06-01), Shirai
patent: 5512771 (1996-04-01), Hiroki et al.
patent: 5789778 (1996-04-01), Murai
Okumura et al., Source-to-Drain Nonuniformity Doped Channel (NUDC) MOSFET structures for high current Drivability and Threshold Voltage Controllability, IEEE Transaction On Electron Devices, vol. 39, No. 11, Nov. 1992.
Okumura, Y., et al., "A Novel Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET for High Current Drivability and threshold Voltage Controllability", LSI R&D Laboratory, Mitsubishi Electric Corp., 4-1 Mizuhara, Itami, Hyogo, Japan, .COPYRGT. 1990 IEEE.

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