Method of manufacturing semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S303000, C438S257000

Reexamination Certificate

active

07015107

ABSTRACT:
When a dummy sidewall and source and drain regions are once formed and then the dummy sidewall is removed to extend the source and drain regions, the removal of the dummy sidewall is performed after formation of a protective oxide film on a gate electrode and on the major surfaces of the source and drain regions. This efficiently prevents conventional surface roughness of the upper surface of the gate electrode and the impurity region due to the removal of the dummy sidewall.

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patent: 6512266 (2003-01-01), Deshpande et al.
patent: 10-12879 (1998-01-01), None
patent: 2001-168323 (2001-06-01), None
K. Tsuji, et al., “High Performance 50-nm Physical Gate Length pMOSFETs by Using Low Temperature Activation by Re-Crystallization Scheme”, Symposium on VLSI Technology Digest of Technical Papers, 1999, pp. 9-10.
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Bin Yu, et al., 70nm MOSFET with Ultra-Shallow, Abrupt, and Super-Doped S/D Extension Implemented by Laser Thermal Process (LTP), IEEE, 1999, pp. 508-513.
H. Wakabayashi, et al., “45-nm Gate Length CMOS Technology and Beyond Using Steep Halo”, IEEE, 2000, pp. 48-53.

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