Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-12
2004-08-31
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000
Reexamination Certificate
active
06784054
ABSTRACT:
BACKGROUND OF THE INVENTION
FIG. 10
is a cross-sectional view of a conventional stack-type nonvolatile semiconductor memory device disclosed in a document (IEDM 1989, pp583-586).
As shown in
FIG. 10
, the conventional nonvolatile semiconductor memory device has a tunnel insulating film
201
formed of a silicon substrate
200
, source and drain regions
202
a
and
202
b
formed in the silicon substrate
200
, stack cell electrodes
211
including a floating gate electrode
203
formed as a layer over the tunnel insulating film
201
, an oxide-nitride-oxide (ONO) capacitor film
204
and a control gate electrode
205
, a topside protective oxide film
206
a
formed over the stack cell electrodes
211
, and an oxide film sidewall
206
b
formed on side surfaces of the topside protective oxide film
206
a
and the stack cell electrodes
211
. The control gate electrode
205
has a lower electrode layer
205
a
formed of polysilicon and an upper electrode layer
205
b
made of a silicide. The nonvolatile semiconductor device has a memory cell transistor thus constructed.
An interlayer insulating film
209
formed of a silicon oxide film and a bit line
210
extending on the interlayer insulating film
209
are provided on the substrate. One of the source and drain regions
202
a
and
202
b
, i.e., the drain region
202
b
in this semiconductor device, is connected to the bit line
210
by a drain contact. The drain contact in this example of the conventional device is constituted by a contact pad
207
formed of a tungsten silicide on the drain region
202
b
, and a tungsten plug
208
extending through the interlayer insulating film
209
and connecting to the contact pad
207
. The contact pad
207
and the stack cell electrodes
211
are electrically insulated from each other by the topside oxide film
206
a
and the oxide film sidewall
206
b
. The upper surface oxide film
206
a
on the control gate electrode
205
is also used as an etching hard mask when the stack cell electrodes
211
are formed by etching. The oxide film sidewall
206
b
is formed in such a manner that an oxide film formed by deposition is etched back by anisotropic etching so that the oxide film is left on the stack cell electrode
211
and the topside oxide film
206
a.
Therefore the insulation withstand voltage between the stack cell electrodes
211
and the contact pad
207
is determined by the film thickness of the topside oxide film
206
a
and the film thickness of the oxide film sidewall
206
b
on the control gate electrode
205
.
In the thus-constructed conventional semiconductor memory device, the contact pads
207
can be formed in a self-alignment manner in correspondence with the source and drain regions
202
a
and
202
b
. That is, there is no need to provide a margin for positioning between a mask for patterning the stack cell electrodes
211
and a mask for forming the contact holes in which the tungsten plugs
208
are embedded. Therefore the distance between the groups of stack cell electrodes
211
can be reduced. In other words, the margin for alignment of the contact holes in which the tungsten plugs
208
are embedded can be increased. For this reason in particular, this structure is suitable for semiconductor device processes of finer rule.
In the process of fabricating the stack-type nonvolatile semiconductor device, however, a plurality of cleaning steps are performed after formation of the topside oxide film
206
a
on the control gate electrode
205
and before deposition for forming the sidewall oxide film.
For example, resist separation and cleaning are performed after ion implantation for forming the source and drain regions, and cleaning is performed before deposition for forming the sidewall oxide film. The silicon oxide film or other materials exposed on the substrate are not substantially etched by one step for such cleaning. However, they are etched to some extent by a plurality of steps for such cleaning. That is, the exposed portion of the topside protective film
206
a
on the control gate electrode
204
is reduced by the plurality of cleaning steps.
FIGS. 9A
,
9
B, and
9
C are cross-sectional views showing steps of forming the semiconductor device described in the above-mentioned document.
FIGS. 9A
,
9
B, and
9
C show only steps after etching on the exposed portion of the topside oxide film
206
a.
As shown in
FIG. 9A
, the topside oxide film
206
a
on the control gate electrode
205
is reduced from the shape before cleaning indicated by the broken line in the figure so that each of the thickness and the width thereof is smaller.
Thereafter, in the step shown in
FIG. 9B
, an oxide film for forming the sidewall is deposited on the substrate and is then etched back by anisotropic etching to form the oxide film sidewall
206
b
on the side surfaces of the stack cell electrodes
211
and the on-gate protective film
206
a
. The oxide film sidewall
206
b
thereby formed is thinner in its portion Redge located above the upper end edge of the control gate electrode
205
.
In the step shown in
FIG. 9C
, a tungsten silicide film is deposited on the substrate and contact pads
207
are formed by patterning from the tungsten silicide film. Further, interlayer insulating film
209
is deposited on the substrate, contact holes are formed through interlayer insulating film
209
so that they can reach the contact pad
207
, and tungsten plugs
208
are formed so as to fill the contact holes. At this time, since the portion of the oxide film sidewall
206
a
is thinner, there is a possibility of the insulation withstand voltage between the contact pad
207
and the control gate electrode
205
being reduced.
In particular, in the nonvolatile semiconductor memory device having stack cell electrodes, because the upper end edge of the control gate electrode
205
to which a high voltage is applied is acute, and has electric field concentrated thereon electric breakdown can occur easily at the corresponding portion Redge, so that the reliability of the semiconductor device is low.
To solve this problem, the method of increasing the film thickness of the oxide film sidewall
206
b
may be used. However, if the film thickness of the oxide film sidewall
206
b
is reduced, the area of contact between the source or drain region
202
a
or
202
b
and the contact pad
207
deposited between the adjacent pair of the groups of stack cell electrodes
211
is reduced, resulting in an increase in the contact resistance between the source and drain regions
202
a
and
202
b.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a stack-type nonvolatile semiconductor memory device including a memory cell transistor having contacts formed between groups of stack cell electrodes in a self-alignment manner to be connected to source and drain regions, the method enabling the semiconductor device to have a higher insulation withstand voltage by using a means for limiting the reduction in thickness of a portion of the insulating film between the contact pad and the control gate electrode.
To achieve the above-described object, according to the present invention, there is provided a method of manufacturing a semiconductor device including a memory cell transistor having stack cell electrodes, the method including a step (a) of forming on a semiconductor substrate in turn from bottom to top, a gate insulating film, a first conductor film, an intermediate insulating film, and a second conductor film, a step (b) of implanting ions of an impurity in the second conductor film, a step (c) of depositing a protective insulating film on the second conductive film after the step (b), a step (d) of performing, after the step (c), a heat treatment for activating the impurity implanted in the second conductor film; a step (e) of performing, after the step (d), patterning in turn the protective insulating film, the second conductor film, the intermediate insulating film and the first conductor on one film and on another to form the stack cell electr
Arai Masatoshi
Nitta Toshinari
Booth Richard A.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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