Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2002-10-15

2004-06-22

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S680000

Reexamination Certificate

active

06753222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device in which a non-volatile semiconductor memory, such as a flash memory, and a standard semiconductor device of MOS-type are formed on the same substrate.
2. Description of the Related Art
Hereinafter, a conventional method for manufacturing a semiconductor device provided with a non-volatile semiconductor memory and a semiconductor device will be described with reference to the drawings.
FIGS. 8A
to
12
B are cross-sectional views illustrating the steps in a conventional method for manufacturing the semiconductor device. In
FIGS. 8A
to
12
B, a region where the non-volatile semiconductor memory is to be formed is indicated as a memory region R
mem
and a region where the standard semiconductor device is to be formed is indicated as a logic region R
logic
.
First, as shown in
FIG. 8A
, an insulating film
2
, for separating the non-volatile semiconductor memory and the semiconductor device, and a p-well
3
are formed on a p-type silicon substrate
1
. Next, a first insulating film
4
, a first polysilicon film
5
, and a second insulating film
6
are formed in an active region of the p-type silicon substrate
1
successively.
Then, as shown in
FIG. 8B
, using a resist pattern
7
as a mask, the second insulating film
6
and the first polysilicon film
5
on the logic region R
logic
are removed by etching.
Further, as shown in
FIG. 8C
, a third insulating film
8
is formed by oxidizing the substrate surface in the logic region R
logic
. Thereafter, a second polysilicon film
9
is formed. The thickness of the second polysilicon film
9
at this time is about 200 nm, for example.
In general, the second insulating film
6
has a three-layer structure including a silicon oxide film/silicon nitride film (Si
3
N
4
)/silicon oxide film, although this structure is not specifically illustrated in the drawings. The silicon oxide film at the top of the second insulating film
6
is formed by the thermal oxidation performed when forming the third insulating film
8
in the logic region R
logic
.
Subsequently, as shown in
FIG. 9A
, the second polysilicon film
9
, the second insulating film
6
, the first polysilicon film
5
, and the first insulating film
4
in the memory region R
mem
are etched using a resist pattern
10
as a mask. As a result, a control gate electrode
9
a
, a capacitor insulating film
6
a
, a floating gate electrode
5
a
, and a tunnel insulating film
4
a
are formed, respectively.
Then, as shown in
FIG. 9B
, a silicon oxide film
11
is formed on the entire surface of the p-type silicon substrate
1
by chemical vapor deposition (CVD) or thermal oxidation. The thickness of the silicon oxide film
11
at this time is about 20 nm, for example.
Next, as shown in
FIG. 9C
, using a resist pattern
12
as a mask, ion implantation
13
is performed for forming a source of the non-volatile semiconductor memory. As a result, a high concentration source region
14
is formed.
After that, as shown in
FIG. 10A
, using a resist pattern
15
as a mask, ion implantation
16
is performed for forming a drain of the non-volatile semiconductor memory. As a result, a high concentration drain region
17
is formed. The silicon oxide film
11
has been formed so that it can serve as a protective oxide film for preventing the tunnel insulating film
4
a
and capacitor insulating film
6
a
from being damaged by the ion implantations for forming the source and the drain of the non-volatile semiconductor memory on the side faces of the gate electrode of the non-volatile semiconductor memory.
The silicon oxide film
11
is then removed by etching as shown in FIG.
10
B. After that, a resist pattern
18
for forming a gate electrode of the semiconductor device in the logic region R
logic
is formed as shown in FIG.
10
C.
Subsequently, as shown in
FIG. 11A
, the second polysilicon film
9
in the logic region R
logic
is etched using the resist pattern
18
as a mask. As a result, a gate electrode
9
b
of the semiconductor device is formed. After that, the resist pattern
18
is removed. Then, using another resist pattern (not shown) that exposes the logic region R
logic
, ion implantation for forming a low concentration drain region
32
and a low concentration source region
33
is performed in the logic region R
logic
. After that, this resist pattern is removed. This brings about the state as shown in FIG.
11
B.
Next, as shown in
FIG. 12A
, a silicon oxide film
21
as an insulating material is formed on the entire surface of the p-type silicon substrate
1
by CVD so that source and drain regions of the semiconductor device in the logic region R
logic
to be formed later will have an LDD structure.
Thereafter, as shown in
FIG. 12B
, the silicon oxide film
21
is etched by anisotropic etching until the upper face of a first gate
19
(see
FIG. 11B
) in the memory region R
mem
and the upper face of a second gate
20
(see
FIG. 11B
) in the logic region R
logic
are exposed. As a result, a side-wall oxide film
22
made of silicon oxide film
21
is formed on the side walls of the first gate
19
and the second gate
20
. After that, the semiconductor device in the logic region R
logic
is subjected to necessary ion implantations (for forming a high concentration source region
35
and a high concentration drain region
34
) and wiring (not shown) to obtain a desired semiconductor device.
However, in the above-mentioned conventional method for manufacturing a semiconductor device, with the miniaturization of elements used in the semiconductor device, new problems arise as follows.
The first problem is as follows. The thickness of the resist pattern
18
shown in
FIG. 10C
has been made thinner in order to form a minute pattern. For example, when forming a pattern of 0.25 &mgr;m or less by photolithography using a KrF excimer laser, the thickness of the resist pattern
18
is in a range from 0.5 to 0.7 &mgr;m.
In this case, as shown in
FIG. 10C
, since the logic region R
logic
substantially is flat, the thickness of the resist pattern
18
formed by photolithography can remain in a range from 0.5 to 0.7 &mgr;m in the logic region R
logic
. In contrast, in the memory region R
mem
, the resist pattern
18
cannot have a uniform thickness since the laminated-type gate electrode pattern already has been formed. The resist pattern
18
has a small thickness, particularly above the gate electrode pattern.
Further, as shown in
FIG. 11A
, the second polysilicon film
9
is etched by dry etching using the above-mentioned resist pattern
18
as a mask. However, during the etching, since the selective ratio of the polysilicon film to the resist pattern generally is low, the resist pattern covering the electrode pattern in the memory region R
mem
is removed before the etching of the gate electrode pattern in the logic region R
logic
is completed. Accordingly, although the etching step as a whole is not yet completed, the electrode pattern itself is exposed in the memory region R
mem
. This leads to a problem that the control gate electrode
9
a
included in the electrode pattern in the memory region R
mem
is etched to have an abnormal shape, resulting in a defective pattern.
The second problem is as follows. In the logic region R
logic
, the second gate of the semiconductor device is formed and the ion implantation for forming the low concentration drain region
32
is performed, as shown in
FIGS. 11A and 11B
. However, in a series of steps in which the formation of the resist pattern and the removal thereof are repeated, since a cleaning step is performed every time after the formation or the removal is completed, the surface of the high concentration source region
14
and the surface of the high concentration drain region
17
may be worn away by these cleaning steps. This may reduce the current flowing though the non-volatile semiconductor memory and interfere with a stable supply of current in the non-volatile semiconductor memor

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