Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2002-10-15

2004-02-24

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S257000, C438S275000

Reexamination Certificate

active

06696329

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-078419, filed on Mar. 20, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a flash memory and a logic circuit or the like having the flash memory on board.
2. Description of the Related Art
In a nonvolatile memory such as a flash memory, as shown in
FIG. 13
, a memory cell array region
101
in which floating-gate type memory cells
103
are arranged in a matrix form and a peripheral transistor region
102
including a logic circuit (not shown) formed on the periphery of the memory cell array region
101
for controlling the operation of the memory cells
103
and the like are provided. In each of the memory cells
103
, a control gate CG, a floating gate FG, a source diffusion layer S, and a drain diffusion layer D are provided. The control gate CG is shared by a plurality of memory cells
103
arranged in a direction in which the control gate CG itself extends. Similarly, the source diffusion layer S is shared by the plurality of memory cells
103
arranged in the direction in which the control gate CG extends. The source diffusion layer S is also shared by a plurality of memory cells
103
arranged perpendicularly to the direction in which the control gate CG extends. The drain diffusion layer D of each of the memory cells
103
is connected to the same bit line (not shown). In the logic circuit, a plurality of MOS transistors
104
and capacitors (not shown) and the like are formed. The MOS transistor
104
is provided with a source/drain diffusion layer SD and a gate electrode G.
Such a nonvolatile memory is manufactured by the following method.
FIGS. 14A and 14B
to
FIGS. 32A and 32B
are sectional views showing a conventional method of manufacturing a nonvolatile memory in the order of process steps. Incidentally,
FIG. 14A
to
FIG. 32A
are sectional views taken along the line I—I in
FIG. 13
, and
FIG. 14B
to
FIG. 32B
are sectional views taken along the line II—II in FIG.
13
.
First, as shown in FIG.
14
A and
FIG. 14B
, an element isolation insulating film
2
a
which defines the memory cell array region
101
and the peripheral transistor region
102
, and element isolation insulating films
2
b
which define the memory cells
103
are formed in the surface of a semiconductor substrate
1
such as a P
+
silicon substrate. The element isolation insulating films
2
a
and
2
b
can be formed, for example, by an STI (Shallow trench isolation) or LOCOS (Local oxidation of silicon) method.
Then, as shown in FIG.
15
A and
FIG. 15B
, an N-well
1
a
is formed on the surface of the semiconductor substrate
1
in the peripheral transistor region
102
, and thereafter a tunnel oxide film
3
is formed on the surface of the semiconductor substrate
1
in each of element forming regions.
Subsequently, as shown in FIG.
16
A and
FIG. 16B
, a polycrystalline silicon film
4
is formed on the entire surface. A resist film
5
is formed on the polycrystalline silicon film
4
, and openings
5
a
are formed in regions of the resist film
5
which match with the element isolating films
2
b
by photolithography technology. The polycrystalline silicon film
4
is patterned by etching the polycrystalline silicon film
4
with the resist film
5
as a mask.
Thereafter, as shown in FIG.
17
A and
FIG. 17B
, the resist film
5
is removed, and an insulating film
6
is formed on the entire surface.
Subsequently, as shown in FIG.
18
A and
FIG. 18B
, a resist film
7
which allows the peripheral transistor region
102
to be exposed is formed.
As shown in FIG.
19
A and
FIG. 19B
, the insulating film
6
, the polycrystalline silicon film
4
, and the tunnel insulating film
3
in the peripheral transistor region
102
are removed by etching with the resist film
7
as a mask.
As shown in FIG.
20
A and
FIG. 20B
, the resist film
7
is removed, and a gate insulating film
8
is formed on the surface of the well
1
a
in the element forming region of the peripheral transistor region
102
. Moreover, a polycrystalline silicon film
9
and a silicon nitride film
10
as an antireflection film are formed in sequence on the entire surface.
Thereafter, as shown in FIG.
21
A and
FIG. 21B
, a resist film
11
for covering each of regions where the control gate electrodes of the memory cells
103
are formed and each of regions where the gate electrodes of the MOS transistors
104
are formed is formed on the silicon nitride film
10
.
Subsequently, as shown in FIG.
22
A and
FIG. 22B
, the silicon nitride film
10
and the polycrystalline film
9
are removed with the resist film
11
as a mask.
As shown in FIG.
23
A and
FIG. 23B
, the resist film
11
is removed, and a resist film
12
which allows the memory cell array region
101
to be exposed is formed.
As shown in FIG.
24
A and
FIG. 24B
, the insulating film
6
and the polycrystalline film
4
are removed with the resist film
12
and the silicon nitride film
10
as the antireflection films as masks.
Thereafter, as shown in FIG.
25
A and
FIG. 25B
, arsenic is doped as an N-type impurity into the surface of the semiconductor substrate
1
in a self-alignment manner by an impurity doping technique, so that a source diffusion layer
13
S and a drain diffusion layer D are formed. Furthermore, the resist film
12
is removed, and phosphorous is doped into only the source diffusion layer
13
S by the impurity doping technique with a resist film (not shown) in which an opening is formed only in a region matching with the source diffusion layer
13
S as a mask.
Subsequently, as shown in FIG.
26
A and
FIG. 26B
, the resist film
12
is removed, and a resist film
14
which allows the peripheral transistor region
102
to be exposed is formed. A low-concentration diffusion layer
15
is then formed by doping a P-type impurity into the surface of the well
1
a
in the self-alignment manner by means of the impurity doping technique.
As shown in FIG.
27
A and
FIG. 27B
, the resist film
14
is removed, and a silicon oxide film (not shown) is formed on the entire surface, for example, by a chemical vapor deposition (CVD) method. By subjecting this silicon oxide film to anisotropic etching, a sidewall insulating film (sidewall spacer)
16
is formed on each side of the silicon nitride film
10
, the polycrystalline silicon film
9
, the insulating film
6
, and the polycrystalline silicon film
4
in the memory cell array region
101
and the silicon nitride film
10
and the polycrystalline silicon film
9
in the peripheral transistor region
102
.
Subsequently, as shown in FIG.
28
A and
FIG. 28B
, a silicon oxide film
17
is formed on the surface of each of the source diffusion layer
13
S, the drain diffusion layer
13
D, and the low concentration diffusion layer
15
by surface oxidation. On this occasion, the thickness of the silicon oxide film
17
formed on the surface of the source diffusion layer
13
S, into which the higher-concentration impurity is doped, is largest due to oxidation enhanced diffusion (enhanced oxidation).
Thereafter, as shown in FIG.
29
A and
FIG. 29B
, the silicon nitride film
10
is removed by wet processing. On this occasion, the silicon oxide film
17
is formed on the surface of each of the source diffusion layer
13
S, the drain diffusion layer
13
D, and the low-concentration diffusion layer
15
, and hence these diffusion layers are not damaged.
Subsequently, as shown in FIG.
30
A and
FIG. 30B
, after a resist film
18
which allows the peripheral transistor region
102
to be exposed is formed, a high-concentration diffusion layer
19
is formed by doping a p-type impurity with a higher concentration than when the low-concentration diffusion layer
15
is formed into the surface of the semiconductor substrate
1
in the self-alignment manner by the impurity doping technique

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