Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-02
2003-12-23
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S229000
Reexamination Certificate
active
06667206
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which can reduce an etching damage caused by removal of a resist.
2. Description of the Background Art
When a size of an MOSFET (Metal Oxide Silicon Field Effect Transistor) is reduced, a channel resistance is dropped. In order to obtain a transistor having a high driving capability, therefore, a parasitic resistance should be reduced as much as possible. A step of removing a resist to be used for a photolithographic process offers a problem.
While the resist is removed by etching, a semiconductor substrate is also etched slightly. In recent years, an MOSFET having a gate length of approximately 0.1 &mgr;m has been developed through a reduction in a size. In such an MOSFET, however, a depth of a source-drain layer is also reduced. Thus, the slight etching of the semiconductor substrate cannot be disregarded.
In particular, an N-channel MOSFET (which will be hereinafter referred to as an NMOS transistor) has a lower channel resistance than that of a P-channel MOSFET (which will be hereinafter referred to as a PMOS transistor). Therefore, when the depth of the source-drain layer is further reduced due to the etching of the semiconductor substrate so that the parasitic resistance is slightly increased, an operating characteristic of the transistor is affected, which is not negligible.
In a conventional art, however, the etching of the semiconductor substrate caused by the removal of the resist has not been particularly recognized as a problem. For example, in a CMOS (Complementary MOS) transistor using a combination of the NMOS transistor and the PMOS transistor, the NMOS transistor and the PMOS transistor are formed adjacently to each other. However, the NMOS transistor has not been considered especially.
A conventional method of manufacturing a CMOS transistor will be described below with reference to
FIGS. 42
to
49
.
At a step shown in
FIG. 42
, first of all, an element isolating film
2
is selectively formed in a surface of a silicon substrate
1
to define an NMOS region NR and a PMOS region PR which form an NMOS transistor and a PMOS transistor, respectively. Then, an N well region NW containing an N-type impurity and a P well region PW containing a P-type impurity are formed in the surface of the silicon substrate
1
corresponding to the NMOS region NR and the PMOS region PR, respectively. Thereafter, a gate insulating film
3
is formed on the silicon substrate
1
and a polysilicon film
4
is formed on the gate insulating film
3
.
Next, a resist (not shown) is provided on the polysilicon film
4
at a step shown in FIG.
43
. The resist is then subjected to patterning by photolithography so that a resist mask is formed. Thereafter, the polysilicon film
4
is subjected to the patterning by using the resist mask. Thus, gate electrodes
41
and
42
are formed on the NMOS region NR and the PMOS region PR, respectively.
At a step shown in
FIG. 44
, subsequently, a resist mask R
1
is formed to cover the PMOS region PR by the photolithography and an N-type impurity ion is implanted into the silicon substrate
1
by using the gate electrode
41
as an implantation mask in the NMOS region NR. Consequently, a pair of extension layers
51
are formed in the surface of the silicon substrate
1
. The extension layers
51
are provided opposite to each other to interpose a region of the silicon substrate
1
provided under the gate electrode
41
therebetween. The region of the silicon substrate
1
provided under the gate electrode
41
acts as a channel region.
The extension layer is an impurity introducing layer formed to have a shallower junction than that of a main source-drain layer to be formed later, has the same conductivity type as that of the main source-drain layer, and functions as a source-drain layer. Therefore, the extension layer should be referred to as a source-drain extension layer but it will be referred to as an extension layer for convenience.
After the resist mask R
1
is removed, a resist mask R
2
is formed to cover the NMOS region NR by the photolithography and a P-type impurity ion is implanted into the silicon substrate
1
by using the gate electrode
42
as an implantation mask in the PMOS region PR so that a pair of extension layers
52
are formed in the surface of the silicon substrate
1
at a step shown in FIG.
45
. The extension layers
52
are provided opposite to each other to interpose a region of the silicon substrate
1
provided under the gate electrode
42
therebetween. The region of the silicon substrate
1
provided under the gate electrode
42
acts as a channel region.
After the resist mask R
2
is removed, a silicon oxide film (not shown) is formed to cover the whole surface of the silicon substrate
1
and is then removed by anisotropic etching together with the gate insulating film
3
provided over the silicon substrate
1
on the outside of side surfaces of the gate electrodes
41
and
42
such that it remains in only side wall portions of the gate electrodes
41
and
42
at a step shown in FIG.
46
. Thus, a side wall protective film (side wall insulating film)
6
is formed.
The side wall protective film
6
is also formed on the gate insulating film
3
provided over the silicon substrate
1
on the outside of the side surfaces of the gate electrodes
41
and
42
, and the gate insulating film
3
and the side wall protective film
6
form a two-layered structure. For simplicity, the side wall protective film
6
having a single layer is shown in and after FIG.
46
.
At a step shown in
FIG. 47
, next, a resist mask R
3
is formed to cover the PMOS region PR by the photolithography and an N-type impurity ion is implanted into the silicon substrate
1
by using the gate electrode
41
and the side wall protective film
6
as implantation masks in the NMOS region NR. Thus, a pair of source-drain layers
71
are formed in the surface of the silicon substrate
1
.
After the resist mask R
3
is removed, a resist mask R
4
is formed to cover the NMOS region NR by the photolithography and a P-type impurity ion is implanted into the silicon substrate
1
by using the gate electrode
42
and the side wall protective film
6
as implantation masks in the PMOS region PR at a step shown in FIG.
48
. Consequently, a pair of source-drain layers
72
are formed in the surface of the silicon substrate
1
.
At a step shown in
FIG. 49
, subsequently, a refractory metal film such as tungsten, cobalt or titanium is formed to cover the whole surface of the silicon substrate
1
and is changed into a silicide by a high temperature treatment. Thus, a silicide film
10
is formed in portions where exposed surfaces of the silicon substrate
1
and the gate electrodes
41
and
42
are provided in contact with the refractory metal film. Then, the refractory metal film which has not been changed into the silicide is removed. Thus, a CMOS transistor
90
shown in
FIG. 49
is obtained.
As described above, in the conventional manufacturing method, the extension layer
51
in the NMOS region NR is etched twice at the steps of removing the resist masks R
1
and R
2
and the gate insulating film
3
cannot prevent the etching of the extension layer
51
. At the steps of removing the resist masks R
3
and R
4
, the source-drain layer
71
is subjected to the etching in place of the extension layer
51
.
As described above, the extension layer is formed more shallowly than the main source-drain layer. Therefore, the extension layer is affected more remarkably by the etching of the silicon substrate
1
than the main source-drain layer. In addition, the NMOS transistor has a lower channel resistance and is more affected by an increase in a resistance of a diffusion layer to be the parasitic resistance than the PMOS transistor due to a difference in a mobility of a carrier to be used.
In the conventional method of manufacturing a semicondu
Renesas Technology Corp.
Trinh Michael
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