Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2002-07-01

2003-12-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C257S335000

Reexamination Certificate

active

06670252

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an MISFET (Metal Insulator Semiconductor Field Effect Transistor).
2. Description of the Background Art
FIGS. 62
to
65
are views showing a process for manufacturing the MISFET. As shown in
FIG. 62
, first of all, an impurity implantation IP
7
is carried out over a surface of a semiconductor substrate
1
provided with an isolation region
2
and an MIS gate structure (a multilayer structure of a gate electrode and a gate insulating film)
3
. Consequently, an LDD (Lightly Doped Drain) region
4
is formed.
Next, an insulating film
5
such as a silicon oxide film is formed on the semiconductor substrate
1
(
FIG. 63
) and is etched. Consequently, a side wall
5
a
is formed on both side surfaces of the MIS gate structure
3
(FIG.
64
).
Then, an impurity implantation IP
8
is carried out over the surface of the semiconductor substrate
1
again. Consequently, a source/drain region
6
is formed (FIG.
65
).
In the method of manufacturing a semiconductor device according to the conventional art, the impurity implantation is to be carried out in each of the step of forming the LDD region
4
and the step of forming the source/drain region
6
. Therefore, the manufacturing process is complicated.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the number of impurity implantations.
According to the present invention, a method of manufacturing a semiconductor device includes the following steps of (a) to (d). At the step (a), a semiconductor substrate having an MIS (Metal Insulator Semiconductor) gate structure formed on a surface is prepared. At the step (b), a buffer film for reducing a quantity of an impurity implantation is provided in a portion which is adjacent to the MIS gate structure over the surface of the semiconductor substrate. At the step (c), an impurity is implanted into the semiconductor substrate, through the buffer film in a portion in which the buffer film is provided, in a predetermined region including the buffer film. At the step (d), the buffer film is removed.
The impurity implantation is carried out over the semiconductor substrate, through the buffer film in the portion in which the buffer film is provided, in the predetermined region including the buffer film. Accordingly, in the case in which the buffer film is provided in a part of the predetermined region, an impurity concentration is reduced in the portion in which the impurity implantation is carried out through the buffer film, while the impurity concentration is increased in a portion in which the buffer film is not provided. Consequently, a plurality of regions having different impurity concentrations can be formed as a source/drain of an MISFET by a one-time impurity implantation so that the number of impurity implantations can be reduced.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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