Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2001-11-26

2003-01-07

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S341000, C438S412000, C438S430000, C438S442000, C438S481000

Reexamination Certificate

active

06503799

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and especially to a method of forming an element isolation insulating film for element isolation.
2. Description of the Background Art
Semiconductor integrated circuits are becoming denser and at the same time, they have accomplished enhanced speed and reduced power supply voltage. Especially in advanced integrated logic circuits including an MPU (Micro Processing Unit), transistor performance and current driving capability for each channel width or, in other words, per unit area have been enhanced in achieving both the enhanced speed and reduced power supply voltage at the same time.
Transistors with higher current driving capability require a smaller area to obtain a sufficient output current and thus can achieve larger packing densities.
On the other hand, as an element isolation technique for electrically isolating a number of elements from one another, trench isolation has been adopted to achieve further improvements in the scale of integration. The trench isolation is a technique for electrically isolating elements by filling a trench formed between each element with an insulator, which with improvements in burying technique, allows the formation of a narrower, deeper element isolation insulating film.
Here, the width of the element isolation insulating film, i.e., the dimension in a direction to define the isolation spacing, is restricted by the amplitude of the power supply voltage and cannot be reduced by the neglect of the power supply voltage.
It is, however, not easy to decrease the power supply voltage and under the present circumstances, a reduction of the power supply voltage has not so much been advanced as the progress of reducing the width (hereinafter referred to a “separation width”) of the element isolation insulating film. From this, a further reduction in the separation width is not easy, which becomes one of the factors that prevent the improvement of integration.
FIG. 20
is a cross-sectional view illustrating part of a conventional semiconductor device in manufacturing process. In
FIG. 20
, an element isolation insulating film
30
made of a silicon oxide film is selectively located in the main surface of a semiconductor substrate
1
. The element isolation insulating film
30
has a tapered cross-sectional shape that narrows with approach from the main surface side of the semiconductor substrate
1
toward its bottom surface, the shape being suitable for the process of filling the silicon oxide film.
Hereinbelow, a method of manufacturing the element isolation insulating film
30
will be set forth with reference to
FIGS. 21
to
23
, which are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
In the step of
FIG. 21
, a silicon oxide film
3
and a silicon nitride film
4
are sequentially deposited over the whole main surface of the semiconductor substrate
1
and a photoresist mask (not shown) is selectively formed on a region where the element isolation insulating film is formed. Using the photoresist mask, the silicon nitride film
4
and the silicon oxide film
3
are selectively removed by anisotropic etching. After removal of the photoresist mask, a trench
2
is selectively formed by anisotropic etching with the silicon nitride film
4
as a mask.
In the step of
FIG. 22
, after etching damage is eliminated by a technique such as thermal oxidation of the trench
2
, a silicon oxide film
20
is formed over the whole surface by CVD so that the trench
2
is filled with the silicon oxide film
20
. The surface of the silicon oxide film
20
is then planarized by CMP (Chemical-Mechanical Polishing) using the silicon nitride film
4
as a stopper, so that the silicon oxide film
20
is left only in the trench
2
.
After that, the silicon nitride film
4
is removed and with the silicon oxide film
3
left as shown in
FIG. 23
, the formation of well region and ion implantation for determination of the threshold voltage of transistors are performed.
Subsequent removal of the silicon oxide film
3
completes the element isolation insulating film
30
shown in FIG.
20
.
Thereafter, a gate electrode, source/drain regions, and the like are formed in each active region defined by the element isolation insulating film
30
, whereby a semiconductor element such as a MOSFET is formed. Such semiconductor elements are connected through a wiring layer, which completes a semiconductor device.
Since the element isolation insulating film in the conventional semiconductor device is tapered toward its bottom as above described and the width of the bottom surface, which determines the separation capability, is narrowest, the only way to obtain a sufficient separation capability is by increasing the width of the upper portion or by deepening the trench.
Deepening the trench, however, imposes limitations on the amount of reduction of the separation width in view of the burying technique for insulating film and consequently prevents the reduction in the size of semiconductor device.
One of measures to resolve part of such a device miniaturization problem is disclosed in U.S. Pat. No. 5,915,192. The technique disclosed is to widen a lower portion of the element isolation insulating film by isotropic etching thereby to increase the effective separation width.
FIG. 24
is a schematic diagram of a configuration disclosed in U.S. Pat. No. 5,915,192. In
FIG. 24
, a trench is located in the surface of the semiconductor substrate
1
and an insulating film is buried therein to form an element isolation insulating film
40
. The trench has an expanded portion EP forming the lower portion of an oval cross-sectional shape and an opening OP formed in the main surface of the semiconductor substrate
1
in communication with the expanded portion EP and having a smaller width than the expanded portion EP.
The element isolation insulating film
40
of such a shape is characterized by its sufficient separation capability resulting from the wide bottom surface, but when an insulating film is buried in the trench, a great void BD may be formed in the expanded portion EP as shown in FIG.
24
. The void BD is a residual gap not filled with the insulating film after the process of filling the trench and is expected to be formed in the central portion of the expanded portion EP so as to be enclosed with the insulating film. The formation of such a void BD can cause a problem of inhibiting the uniformity of ion implantation. This problem will be considered with reference to
FIGS. 25
to
28
.
FIGS. 25 and 26
illustrate an element isolation insulating film
40
A formed for element isolation and an element isolation insulating film
40
B formed for well isolation, respectively. The element isolation insulating films
40
A and
40
B are basically identical to the element isolation insulating film
40
shown in
FIG. 24
, but for convenience's sake, they are denoted by the different reference numerals.
As shown in
FIG. 25
, after the element isolation insulating film
40
A is formed in the surface of the semiconductor substrate
1
, a P-type impurity PI is doped by ion implantation for formation of a well region, in this case a P-type well region.
Also as shown in
FIG. 26
, after the element isolation insulating film
40
B is formed in the surface of the semiconductor substrate
1
, a P-type impurity PI and an N-type impurity NI are doped by ion implantation for formation of well regions, in this case P- and N-type well regions, respectively.
For the sake of simplicity,
FIGS. 25 and 26
schematically show only the ion implantation in the vicinity of the element isolation insulating films
40
A and
40
B.
The void BD, as compared with the insulating film (silicon oxide film) and the semiconductor substrate (silicon substrate), has substantially no capability to block implant ions. In the element isolation insulating films
40
A and
40
B, therefore, the speed of implant ions passing through the voi

Affiliated with

Also associated with

Rating

Method of manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3025228