Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-01
2002-10-29
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S275000
Reexamination Certificate
active
06472259
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device. More specifically, the present invention relates to a method of manufacturing a semiconductor device comprising a nonvolatile memory transistor of a stacked gate structure having a floating gate and a control gate, and a MOS transistor of a single gate structure.
DESCRIPTION OF THE RELATED ART
A method for manufacturing EEPROM having a high-voltage transistor (for example, a MOS transistor is available) is described in, for example, U.S. Pat. No. 4,851,361. According to this ordinary method, an active region is formed in a semiconductor substrate, a thin tunnel region of a nonvolatile memory cell is formed on the semiconductor substrate, and a first polysilicon layer is then deposited on the whole surface of the semiconductor substrate. Subsequently, the first polysilicon layer is processed to form a floating gate electrode of the nonvolatile memory cell. Further, after a capacitive insulation film, a gate oxide film of a high-voltage transistor and a gate oxide film of a logic circuit portion are formed, a second polysilicon layer is deposited on the whole surfaces of the oxide films. And this second polysilicon layer is processed to form a control gate of the memory cell, a gate electrode of the high-voltage transistor and a gate electrode of the logic circuit.
SUMMARY OF THE INVENTION
However, in the above ordinary method of manufacturing the semiconductor device comprising the nonvolatile memory cell such as EEPROM and the logic circuit, there is a difference in level in the deposited second polysilicon layer, which is due to the first polysilicon layer. As a result, there is a need for removing the second polysilicon deposited on the side wall of the difference due to the first polysilicon layer. Thus, conditions have to be set such that side etching occurs by conducting excess etching. In this case, however, the dimensional accuracy of the gate formed by the second polysilicon layer is decreased, and it is difficult to form a fine gate.
Further, since the gate oxide film of the high-voltage transistor and the gate oxide film of the logic circuit portion are formed simultaneously, the gate oxide film has to be formed relatively thick, and it is hard to finely process the logic circuit portion. Therefore, there would be a method in which the gate oxide film of the high-voltage MOS transistor is formed relatively thick and the gate oxide film of the logic circuit portion is formed relatively thin. Nevertheless, this method is undesirable, since the number of steps is increased.
Under the circumstances, one of the objects of the invention is to provide a method of manufacturing a semiconductor device comprising a nonvolatile memory cell such as EEPROM and a logic circuit, in which a finer gate electrode is formed in the logic circuit portion without increasing the number of steps.
The first aspect of the invention is a method for manufacturing a semiconductor device comprising a nonvolatile memory transistor of a stacked gate structure having a floating gate and a control gate, and a MOS transistor of a single gate structure. The method comprises the steps of:
forming a first insulation film on a semiconductor substrate, said first insulation film becoming a gate oxide film of both the nonvolatile memory transistor and the MOS transistor;
forming a first conductive layer on the first insulation film;
removing an area extending in a direction perpendicular to a direction in which the control gate is formed extendedly from the first conductive layer to form a region for separating the floating gate;
forming a second insulation layer on the first conductive layer;
forming a second conductive layer on the second insulation film;
patterning the second conductive layer so as to form the control gate; and
patterning the first conductive layer to form the stacked gate structure and the single gate structure.
The second aspect of the invention is the method for manufacturing the semiconductor device as described in the first aspect, wherein the MOS transistor of the single gate structure includes a high-voltage transistor and a MOS transistor forming a peripheral circuit.
The third aspect of the invention is the method for manufacturing the semiconductor device as described in the second aspect, wherein the step of forming the first insulation film comprises the steps of forming a gate insulation film of a high-voltage transistor, and forming a tunnel oxide film between the floating gate and the substrate and simultaneously forming a gate insulation film of the MOS transistor forming the peripheral circuit.
The fourth aspect of the invention is the method for manufacturing the semiconductor device as described in the first aspect, wherein the floating gate is patterned in self-alignment manner using the second conductive layer constituting the control gate as a mask, in the step of patterning the first conductive layer to form the stacked gate structure.
The fifth aspect of the invention is the method for manufacturing the semiconductor device as described in the first aspect, wherein the first conductive layer and the second conductive layer are made of polysilicon
The sixth aspect of the invention is the method for manufacturing the semiconductor device as described in the first aspect, wherein the method further comprises a step of forming a side wall on the side surface of the control gate after patterning the second conductive layer.
The seventh aspect of the invention is the method for manufacturing the semiconductor device as described in the fifth aspect, wherein the method further comprises a step of forming a first metal silicide layer on the second conductive layer.
The eighth aspect of the invention is the method for manufacturing the semiconductor device as described in the seventh aspect, wherein the method further comprises the steps of:
forming a third insulation film on the first metal silicide layer;
removing the third insulation film, the first metal suicide layer, the second conductive layer and the second insulation film except the control gate portion of the stacked gate structure to form the control gate portion;
forming a side wall on the control gate portion;
forming a second metal silicide layer on the first conductive layer and the third insulation film exposed;
forming a fourth insulation film on the second metal suicide layer; and
etching the first conductive layer using the control gate portion as a mask to form the stacked gate structure in self-alignment manner, while patterning the fourth insulation film, the second metal silicide layer, and the first conductive layer to form the MOS transistor of the single gate structure.
The ninth aspect of the invention is a method for manufacturing a semiconductor device having a nonvolatile memory cell, a capacitor and/or a resistance, and a logic circuit, which method comprises the steps of;
simultaneously forming a tunnel oxide film of the memory cell and a gate oxide film of a MOS transistor of the logic circuit;:
forming a first polysilicon layer on the whole surface of the oxide film;
removing a region for separating a floating gate of the memory cell of the first polysilicon layer;
forming a first insulation film on the first polysilicon layer;
forming a second polysilicon layer on the whole surface of the first insulation film;
forming a second insulation film on the second polysilicon layer;
removing the second insulation film, the second polysilicon layer and the first insulation film except the desired region of the memory cell and the upper electrode region of the capacitor;
forming a third insulation film on the whole surface;
removing the portions of the third insulation film except the lower electrode region of the capacitor and the region of the resistance; and
anisotropically etching the whole surface to form a side wall of a stacked gate of the memory cell.
REFERENCES:
patent: 4851361 (1989-07-01), Schumann et al.
patent: 5075246 (1991-12-01), Re et al.
patent: 5550072
Imai Hisaya
Mochizuki Hidenori
Naito Fumio
Asahi Kasei Microsystems Co. Ltd.
Finnegan Henderson Farabow Garrett & Dunner LLP
Pham Long
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