Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1999-06-04

2002-02-05

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S481000, C438S595000

Reexamination Certificate

active

06344388

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it relates to a method of manufacturing a MOSFET having salicide structure. The present invention also relates to a method of manufacturing a semiconductor device having a plurality of types of semiconductor elements for different applications formed in a single wafer.
2. Description of the Background Art
Background Art 1
FIGS. 46
to
52
are sectional views showing a conventional method of manufacturing a semiconductor device in step order. In particular, these figures successively illustrate steps of manufacturing a MOSFET having a salicide structure. First, element isolation insulative films
102
consisting of silicon oxide are formed on element isolation regions of a silicon substrate
101
, thereafter ion implantation is performed for forming a well, a channel (not shown) and the like, and thereafter a gate oxide film
103
consisting of silicon oxide and a gate electrode
104
consisting of polysilicon are selectively formed on an upper surface of the silicon substrate
101
. Thereafter ion implantation is performed for forming impurity regions (hereinafter referred to as extensions)
105
in the upper surface of the silicon substrate
101
(FIG.
46
).
Then, a silicon oxide film
106
is deposited on the overall surface by CVD, for example, and thereafter a silicon nitride film
107
is deposited on the silicon oxide film
106
(FIG.
47
). Then, the silicon nitride film
107
and the silicon oxide film
106
are etched in this order by anisotropic dry etching having a high etching rate along the depth of the silicon substrate
101
, to expose the upper surface of the silicon substrate
101
. Thus, side walls
110
defined by silicon oxide films
108
and silicon nitride films
109
are formed on side wall portions of the gate electrode
104
(FIG.
48
).
Then, ion implantation is performed through the gate electrode
104
and the side walls
110
serving as masks, to form impurity regions
111
in the exposed upper surface of the silicon substrate
101
. Consequently, source/drain regions
112
defined by the extensions
105
and the impurity regions
111
are formed in the upper surface of the silicon substrate
101
(FIG.
49
).
Then, silicon is grown under conditions having selectivity for a silicon oxide film and a silicon nitride film (this means crystal growth under such conditions that silicon is grown not on a silicon oxide film and a silicon nitride film but on the remaining region) for forming a silicon growth layer
113
on an upper surface of the gate electrode
104
while forming silicon growth layers
114
on the upper surface of the silicon substrate
101
in portions formed with the impurity regions
111
(FIG.
50
).
Then, a cobalt layer
115
is deposited on the overall surface by CVD, for example (FIG.
51
), and thereafter heat treatment is performed in an inert gas atmosphere of nitrogen, argon or the like. Thus, the cobalt layer
115
reacts with the silicon growth layers
113
and
114
, to form cobalt silicide layers
116
and
117
. Thereafter unreacted parts of the cobalt layer
115
are removed (FIG.
52
). A MOSFET having a salicide structure is manufactured through the aforementioned steps. Thereafter the device is completed through a process including a step of forming an interlayer insulative film, a wiring step and the like.
Background Art 2
FIGS. 53
to
57
are sectional views showing another method of manufacturing a semiconductor device in step order. In particular, these figures successively illustrate steps of manufacturing a semiconductor device having a plurality of types of semiconductor elements for different applications formed in a single wafer. First, element isolation insulative films
102
consisting of silicon oxide are formed on element isolation regions of a silicon substrate
101
, thereafter ion implantation is performed for forming a well, a channel (not shown) and the like, and thereafter gate oxide films
103
consisting of silicon oxide and gate electrodes
104
consisting of polysilicon are selectively formed on an upper surface of the silicon substrate
101
. Thereafter ion implantation is performed to form extensions
105
in the upper surface of the silicon substrate
101
(FIG.
53
).
Then, a silicon oxide film
106
is deposited on the overall surface by CVD, for example (FIG.
54
). Thereafter a silicon nitride film
107
is deposited on the silicon oxide film
106
by CVD, for example (FIG.
55
). Thereafter the silicon nitride film
107
and the silicon oxide film
106
are etched in this order by anisotropic dry etching having a high etching rate along the depth of the silicon substrate
101
, to expose the upper surface of the silicon substrate
101
. Thus, side walls
110
a
defined by silicon oxide films
108
and silicon nitride films
109
are formed on side wall portions of the gate electrode
104
in a DRAM part of the silicon substrate
101
, while side walls
110
b
defined by silicon oxide films
108
and silicon nitride films
109
are formed on side wall portions of the gate electrode
104
in a logic part of the silicon substrate
101
(FIG.
56
).
Then, ion implantation is performed through the gate electrodes
104
and the side walls
110
a
and
110
b
serving as masks, to form impurity regions
111
in the exposed upper surface of the silicon substrate
101
. Consequently, source/drain regions
112
defined by the extensions
105
and the impurity regions
111
are formed in the upper surface of the silicon substrate
101
(FIG.
57
). A DRAM-MOSFET and a logic MOSFET are formed on the DRAM part and the logic part of the silicon substrate
101
respectively through the aforementioned steps. Thereafter the device is completed through a process including a step of forming an interlayer insulative film, a wiring step and the like.
Problem related to Background Art 1
In order to increase the operating speed of a MOSFET or improve the high-frequency characteristic thereof, it is also important to reduce gate resistance and source/drain resistance. While the gate resistance is reduced by forming a conductive layer such as the cobalt silicide layer
116
on the gate electrode
104
as in the MOSFET shown in
FIG. 52
, the gate resistance can be further reduced if the width of the cobalt silicide layer
116
can be increased.
As shown in
FIG. 52
, however, the width of the cobalt silicide layer
116
is substantially equal to the gate length in the conventional MOSFET, and hence the gate length must be increased in order to increase the width of the cobalt silicide layer
116
. If the width of the gate electrode
104
is increased in order to increase the gate length, however, the source-to-drain distance is also increased. Consequently, the channel resistance is increased to reduce the driving current for the MOSFET, to result not only in reduction of the operating speed and the high-frequency characteristic of the MOSFET but also in insufficient satisfaction of requirement for refinement of the device.
FIGS. 58 and 59
are sectional views showing parts A and B in
FIG. 50
in an enlarged manner respectively. As hereinabove described, the silicon growth layer
114
is formed by growing silicon on the upper surface of the silicon substrate
101
. At this time, a specific plane orientation influences the growth rate, and hence facets appear on end portions of the silicon growth layer
114
.
FIG. 58
shows a facet
120
a
appearing on an end portion of the silicon growth layer
114
closer to the side wall
110
, while
FIG. 59
shows a facet
120
b
appearing on an end portion of the silicon growth layer
114
closer to the element isolation insulative film
102
. A silicon oxide film
106
a
shown in
FIG. 59
is a part of the silicon oxide film
106
, deposited on the element isolation insulative film
102
, remaining on the side wall portion of the element isolation insulative film
102
in the anisotropic dry etching for forming t

Affiliated with

Also associated with

Rating

Method of manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2954886