Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-29
2002-10-22
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000, C438S656000
Reexamination Certificate
active
06468898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to the method of manufacturing the semiconductor device provided with a dual damascene wiring structure.
2. Description of the Related Art
In LSI (Large Scale Integrated) circuits such as micro-processors, memories and like, there is substantial incentive toward higher levels of integration density and design rules permitting smaller minimum feature sizes for individual circuit components or devices. In other words, as a semiconductor industry moves toward smaller and smaller device dimensions, a greater density of devices per silicon substrate is required. As device dimensions shrink, each of wires (wiring lines) extending from individual active areas also shrinks in width and in wiring pitch, wherein the wiring pitch is a distance between two adjacent wiring lines. Due to this, these wiring lines are closely packed to increase their wiring density. Further, since the wiring density has increased described above, a so-called “multilevel metallization technology” has been developed and employed, wherein a plurality of layers each of which has a wiring line and a thickness are stacked together into a stack to form a semiconductor device.
In the LSI circuits described above, shrinking of the wiring pitch leads to an increase in interwiring capacitance, which considerably affects particularly a high-speed type of LSI circuits in operation speed. In order to prevent the interwiring capacitance from increasing, it is so devised that an interlayer insulation film formed between two adjacent wiring layers is constructed of a low dielectric constant film. Further, operation speed depends on a wiring resistance. In general, heretofore, wiring materials used in the semiconductor device provided with LSI circuits have been aluminum (Al) or an aluminum-based alloy containing aluminum as its main component, wherein aluminum or the aluminum-based alloy is hereinafter referred to as an aluminum-based metal. However, in order to increase operation speed, it is necessary to use a conductive material which is smaller in electric resistance than the aluminum-based metal.
As a result, copper (Cu) which is smaller in electric resistance than the aluminum-based metal has been widely used in place of the aluminum-based metal.
On an other hand, as one of conventional structures adapted for use with a fine wiring line in a multilevel interconnection, there is known a dual damascene wiring structure. In this dual damascene wiring structure: a Cu underlying wiring line is previously formed on a semiconductor substrate; an interlayer insulation film is then formed on the semiconductor substrate through the Cu underlying wiring line; and, both a via hole and a trench for forming an overlying wiring line (hereinafter referred to as an overlying wiring trench) are formed in the interlayer insulation film and filled with Cu (copper) to form a Cu via contact and a Cu overlying wiring line, respectively; whereby the Cu underlying wiring line is electrically connected with the Cu overlying wiring line through the Cu via contact.
FIGS. 7A-7F
and
8
A-
8
E are views showing a series of process steps of a conventional method of manufacturing a semiconductor device provided with the dual damascene wiring structure such as that described above. Hereinbelow, with reference to
FIGS. 7A-7F
and
8
A-
8
E, the conventional method of manufacturing the semiconductor device will be described in order of its process steps.
First, as shown in
FIG. 7A
, a Cu wiring line
51
is formed on a semiconductor substrate (not shown) as an underlying wiring line. Formed on the Cu wiring line
51
by a plasma CVD (chemical vapor deposition) process of a parallel flat plate type is a P—SiN (plasma silicon nitride) film
52
which has a film thickness of approximately 50 nm. After formation of the P—SiN film
52
, an organic polymer film
53
having a film thickness of approximately 400 nm is formed on the P—SiN film
52
by a spin coating process. Then, in an atmosphere of nitrogen gas, the semiconductor substrate is subjected to a baking process which is performed at a temperature of approximately 400° C. for approximately one hour. After that, a P—SiO
2
(plasma silicon oxide) film
54
having a film thickness of approximately 100 nm is formed on the organic polymer film
53
by the plasma CVD process. Here, the P—SiN film
52
, the organic polymer film
53
and the P—SiO
2
film
54
serve as a Cu diffusion barrier film, a low dielectric constant film and an insulation protective film, respectively. Further, the P—SiN film
52
, the organic polymer film
53
and the P—SiO
2
film
54
are stacked into a stack to form an interlayer insulation film.
Next, as shown in
FIG. 7B
, a photoresist is applied to an upper surface of the P—SiO
2
film
54
to form a photoresist film on the P—SiO
2
film
54
. After that, as will be described later, the thus formed photoresist film is patterned to form a first photoresist film
55
which has a pattern for forming a via hole. Then, as shown in
FIG. 7C
, using the first photoresist film
55
as a mask, a dry etching process is performed to selectively remove the P—SiO
2
film
54
. Subsequent to this, as shown in
FIG. 7D
, using the first photoresist film
55
as a mask, a plasma etching process employing an oxygen-based gas is performed to selectively remove the organic polymer film
53
in a manner such that a hole
56
having a width of W
1
and forming a part of the via hole is formed. Further, the first photoresist film
55
is removed by an ashing process when the organic polymer film
53
is selectively removed. In other words, the ashing process of the first photoresist film
55
is performed through an anisotropic plasma ashing treatment.
Next, as shown in
FIG. 7E
, a photoresist is applied to an upper surface of the P—SiO
2
film
54
to form a photoresist film on the P—SiO
2
film
54
. After that, as will be described later, the thus formed photoresist film is patterned to form a second photoresist film
57
which has a pattern for forming an overlying wiring trench for forming an overlying wiring trench
58
. Then, as shown in
FIG. 7F
, using the second photoresist film
57
as a mask, a dry etching process is performed to selectively remove the P—SiO
2
film
54
. Subsequent to this, using the second photoresist film
57
as a mask, an oxygen plasma etching process is performed to selectively remove the organic polymer film
53
in a manner such that the overlying wiring trench
58
which has a width of W
2
(>W
1
) and is smaller in depth than the hole
56
. Further, the second photoresist film
57
is also removed by an ashing process when the organic polymer film
53
is selectively removed, as is in a case of the first photoresist film
55
. In other words, the ashing process of the second photoresist film
57
is performed through anisotropic plasma ashing treatment.
Then, as shown in
FIG. 8A
, by a plasma etching process, the P—SiN film
52
is etched back to selectively expose the Cu wiring line
51
. As a result, the hole
56
extends to a top surface of the Cu wiring line
51
thus exposed, so that a via hole
59
is formed. Then, as shown in
FIG. 8B
, by an ion sputtering process, a TaN (tantalum nitride) film
60
is formed over an entire surface of substrate including both the overlying wiring trench
58
and the via hole
59
. After that, as shown in
FIG. 8C
, by a sputtering process, a Cu seed film
61
having a film thickness of approximately 50 nm is formed on the TaN film
60
.
Next, as shown in
FIG. 8D
, by a plating process, a Cu-plated film
62
having a film thickness of approximately 800 nm is formed on the Cu seed film
61
. After that, as shown in
FIG. 8E
, the Cu-plated film
62
, the Cu seed film
61
and the TaN film
60
, all of which are formed above a top surface of the P—SiO
2
film
54
, are removed by a CMP (chemical mechanical polishing) process, so that the top surface of the
Dang Trung
Kebede Brook
McGinn & Gibb PLLC
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