Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-23
2002-01-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000
Reexamination Certificate
active
06342413
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor device, and in particular, relates to a method of manufacturing a semiconductor device which has a plurality of MIS (Metal Insulator Semiconductor) transistors having various thresholds.
An LSI (Large Scale Integrated circuit) is known as a typical semiconductor device and generally comprises a large number of MOS (Metal Oxide Semiconductor) transistors which are a sort of the MIS transistors and which are superior in integration. Such an MOS LSI is widely applicable to various electronic equipment including an information equipment because manufacturing costs of the MOS LSI can be lowered by increasing a degree of the integration.
Recently, an LSI that memories and logic units (or logic circuits) are merged in a single semiconductor chip and that is categorized into a group called an SOC (System On Chip) was developed and could realize desired functions singly. For example, the LSI is applied to a mobile information apparatus. The LSI for the mobile information apparatus is designed so as to save power consumption and to be operated by the lowest possible voltage, because a power source is a battery in the mobile information apparatus.
In the LSI categorized into the SOC group, each of the logic units is made by a CMOS (Complementary MOS) process and comprises n-type MOS transistors and p-type MOS transistors. The n-type MOS transistors and the p-type MOS transistors have various thresholds so that the LSI carries out the desired functions.
Generally, reduction of a threshold is necessary to heighten an operation speed of a transistor. Moreover, increase of the threshold is necessary to reduce both of leakage current and power consumption of the transistor. Consequently, the n-type and p-type MOS transistors in each of the logic units have the various thresholds according to their purpose.
If the n-type MOS transistors have three levels for their thresholds in the logic unit, three times of a lithography process are necessary to form a well and channel regions of the n-type MOS transistors. Similarly, if the p-type MOS transistors have three levels for their thresholds in the logic unit, additional three times of the lithography process are necessary to form a well and channel regions of the p-type MOS transistors. Thus, a large number of processes are necessary to manufacture the semiconductor device such as the LSI categorized into the SOC group.
In the meantime each MOS transistor has junction capacitance between each of a source region and a drain region and a substrate. In a case where a rapid operation is desired in the MOS transistor, it is desirable that the junction capacitance is the smallest as possible.
SUMMARY OF THE INVENTION
It is therefor an object of this invention to provide a method of manufacturing a semiconductor device which can be reduce the number of times of lithography process.
It is another object of this invention to provide a structure of a semiconductor device which have MOS transistors having various thresholds and which is easy to manufacture.
It is still another object of this invention to provide a structure of a semiconductor device which has MOS transistors and has small junction capacitance between each of a source region and a drain region and a substrate in at least one of the MOS transistors.
Other object of this invention will become clear as the description proceeds.
According to a first aspect of this invention, a semiconductor device has first, second and third MIS transistors on a semiconductor substrate. The first MIS transistor has a first threshold. The second MIS transistor has a second threshold higher than the first threshold. The third MIS transistor has a third threshold higher than the second threshold. A method of manufacturing the semiconductor device comprises the steps of depositing a first mask on the semiconductor substrate at a first area for the first MIS transistor, introducing first impurities into the semiconductor substrate to form wells at second and third areas for the second and the third MIS transistors, successively, introducing second impurities into the wells to form first threshold adjustment regions for the second threshold, depositing a second mask on the semiconductor substrate at the second area for the second MIS transistor after removing the first mask, and introducing third impurities into the semiconductor substrate to form second threshold adjustment regions for the first threshold at the first and the third areas. One of the second threshold adjustment regions serves as a third threshold adjustment region for the third threshold together with one of the first threshold adjustment regions at the third area.
According to a second aspect of this invention, a semiconductor device has first, second and third MIS transistors in a semiconductor substrate. The first MIS transistor has a first threshold. The second MIS transistor has a second threshold higher than the first threshold. The third MIS transistor has a third threshold higher than the second threshold. A method of manufacturing the semiconductor device comprises the steps of defining first, second and third areas corresponding to the first, the second and the third MIS transistors, respectively, on a surface of the semiconductor substrate, depositing a first mask having first and second opening windows corresponding to the second and the third areas, respectively, on the surface of the semiconductor substrate, introducing first impurities into the semiconductor substrate through said first and the second opening windows to form wells at the second and the third areas at the same time, successively introducing second impurities into the wells through the first and the second opening windows to form first threshold adjustment regions for the second threshold at the same time, completely removing the first mask from the surface of the semiconductor substrate, depositing a second mask having third and fourth opening windows corresponding to the first and third areas, respectively, on the surface of the semiconductor substrate, and introducing third impurities into the semiconductor substrate through the third and the fourth opening windows to form second threshold adjustment regions for the first threshold at the same time. One of the second threshold adjustment regions serves as a third threshold adjustment region for the third threshold together with one of the first threshold adjustment regions at the third area.
According to a third aspect of this invention, a semiconductor device has first, second and third MOS transistors having a first conductive type and has fourth, fifth and sixth MOS transistors having a second conductive type different from the first conductive type. The first and the forth MOS transistors forms a first CMOS transistor having a first threshold. The second and the fifth MOS transistors forms a second CMOS transistor having a second threshold higher than the first threshold. The third and the sixes MOS transistors forms a third CMOS transistor having a third threshold higher than the second threshold. A method of the semiconductor device comprises the steps of defining first through sixth areas corresponding to first through sixth MOS transistors, respectively, on a surface of the semiconductor substrate, depositing a first mask having first and second opening windows corresponding to the second and the third areas, respectively, on the surface of the semiconductor substrate, introducing first impurities of the second conductive type into the semiconductor substrate through the first and the third opening windows to form first wells in the second and the third areas at the same time, successively introducing second impurities of the second conductive type into the first wells through the first and the second opening windows to form first threshold adjustment regions for the second threshold at the same time, completely removing the first mask from the surface of the semiconductor substrate, depositing a second mask having t
Imai Kiyotaka
Masuoka Sadaaki
Dang Phuc T.
McGinn & Gibb PLLC
Nelms David
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