Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-02
2002-05-07
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S525000, C438S289000
Reexamination Certificate
active
06383884
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a MOSFET having a gate structure formed by a replacement technique.
2. Description of the Background Art
FIG. 34
is a cross-sectional view of a background art semiconductor device having a gate structure formed by the replacement technique. As shown in
FIG. 34
, the background art semiconductor device comprises: a silicon substrate
101
; a pair of spaced source/drain regions
109
formed in an upper surface of the silicon substrate
101
and defining a channel region (not shown) therebetween in the upper surface of the silicon substrate
101
; a pair of sidewalls
107
and a pair of silicon nitride films
108
which are formed on the upper surface of the silicon substrate
101
so as to overlie the source/drain regions
109
; and a gate structure
106
formed in a recess defined by the upper surface of the silicon substrate
101
over the channel region and side surfaces of the sidewalls
107
. The gate structure
106
comprises a gate oxide film
102
formed on the upper surface of the silicon substrate
101
, and a gate electrode including a polysilicon film
103
formed on the gate oxide film
102
, a barrier metal
104
formed on the side surfaces of the sidewalls
107
and an upper surface of the polysilicon film
103
, and a metal film
105
formed on the barrier metal
104
.
FIGS. 35 through 41
are cross-sectional views showing a method of manufacturing the background art semiconductor device shown in
FIG. 34
in a step-by-step manner. Initially, an isolating insulation film (not shown) is formed in an isolation region of the silicon substrate
101
, and thereafter ion implantation is performed to form a well, a doped channel region and the like (not shown). Then, a silicon oxide film
110
, a polysilicon film
111
and a silicon oxide film
112
are formed by deposition or the like in stacked relation in the order named on the upper surface of the silicon substrate
101
(FIG.
35
).
Next, a photoresist
113
is formed by a photolithographic technique on an upper surface of the silicon oxide film
112
over a region in which a dummy gate electrode is to be formed later (FIG.
36
). Using the photoresist
113
as a mask, the silicon oxide film
112
, the polysilicon film
111
and the silicon oxide film
110
are etched in the order named to expose the upper surface of the silicon substrate
101
. Then, the photoresist
113
is removed. This provides the gate oxide film
102
selectively formed on the upper surface of the silicon substrate
101
, and the dummy gate electrode formed on the gate oxide film
102
and having a multilayer structure including the polysilicon film
103
and a silicon oxide film
114
which are stacked in the order named. Thereafter, using the dummy gate electrode as a mask, ions
115
are implanted into the upper surface of the silicon substrate
101
to form a pair of extension regions
116
(FIG.
37
).
A silicon nitride film is deposited on the entire surface of the resultant structure, and is etched back until the upper surface of the silicon substrate
101
is exposed, to form the sidewalls
107
on side surfaces of the dummy gate electrode. Using the dummy gate electrode and the sidewalls
107
as a mask, ions
117
are implanted into the upper surface of the silicon substrate
101
to form the pair of source/drain regions
109
(FIG.
38
).
A silicon nitride film is deposited on the entire surface of the resultant structure, and is polished until an upper surface of the silicon oxide film
114
is exposed, to form the silicon nitride films
108
(FIG.
39
). Using the silicon nitride films
108
as a mask, the silicon oxide film
114
is etched away to expose the upper surface of the polysilicon film
103
(FIG.
40
). A barrier metal
118
and a metal film
119
are deposited on the entire surface of the resultant structure (FIG.
41
). Next, the barrier metal
118
and the metal film
119
are polished until the upper surface of the silicon nitride films
108
is exposed by a CMP process. This provides the structure shown in FIG.
34
. After the steps of forming an interlayer insulation film and forming an interconnect line and the like, the device is completed.
However, the background art semiconductor device and the method of manufacturing the same present problems to be described below.
Reductions in gate length and in gate resistance are important factors required to increase the operating speed of a MOSFET or to improve the driving capability and high frequency characteristic thereof. The reduction in gate length is attained by forming a narrower photoresist pattern by a photolithographic technique, but there is a limit on the formation of fine patterns because of an exposure limit. For example, if the photoresist
113
having a length L
101
is formed in the step shown in
FIG. 36
, the gate length L
100
of the gate electrode equals the length L
101
as shown in FIG.
34
. Thus, a first problem with the background art semiconductor device and the method of manufacturing the same is that it is impracticable that the gate length which is determined by the exposure limit of the photolithographic technique used in the formation of the photoresist
113
is less than the exposure limit of the photolithographic technique.
On the other hand, the reduction in gate resistance of the background art semiconductor device shown in
FIG. 34
is attained by making the lengths of the barrier metal
104
and the metal film
105
greater than the length of the polysilicon film
103
(equal to the gate length L
100
). However, according to the method of manufacturing the background art semiconductor device in which the lengths of the barrier metal
104
and the metal film
105
are equal to the gate length L
100
, the increase in the lengths of the barrier metal
104
and the metal film
105
requires the increase in the gate length L
100
itself, presenting a second problem in that the driving capability of the MOSFET decreases.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) selectively forming a multilayer structure including a gate insulation film and a dummy gate electrode stacked in the order named on an upper surface of a substrate, the dummy gate electrode having an upper part and a lower part; (b) forming a first insulation film in a side surface of the lower part; (c) forming a pair of source/drain regions in the upper surface of the substrate, with part of the upper surface of the substrate which underlies the gate insulation film lying between the pair of source/drain regions; (d) forming a second insulation film on the upper surface of the substrate overlying the pair of source/drain regions, the second insulation film having a thickness greater than the height of the first insulation film from the upper surface of the substrate, the second insulation film being in contact with the dummy gate electrode; (e) removing the dummy gate electrode while leaving the first insulation film, the step (e) being performed after the step (d); and (f) forming a gate electrode filling a recess defined by the gate insulation film and the first and second insulation films.
Preferably, according to a second aspect of the present invention, in the method of the first aspect, a thermal oxidation reaction proceeds at a lower rate in the upper part than in the lower part in the step (a). The first insulation film is formed by thermally oxidizing the dummy gate electrode in the step (b).
Preferably, according to a third aspect of the present invention, the method of the second aspect further comprises the step of (x) introducing an impurity into the upper surface of the substrate by using the dummy gate electrode as a mask to form an extension region, the step (x) being performed between the steps (a) and (b).
Preferably, according to a fourth aspect of the pre
Horita Katsuyuki
Itoh Yasuyoshi
Kuroi Takashi
Shiozawa Katsuomi
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan H.
Oblon, Spivak, McClelland, Maier & Nuestadt, P.C.
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