Method of manufacturing semiconductor device

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant

Reexamination Certificate

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Reexamination Certificate

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07947585

ABSTRACT:
Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.

REFERENCES:
patent: 4350541 (1982-09-01), Mizushima et al.
patent: 6033963 (2000-03-01), Huang et al.
patent: 6225173 (2001-05-01), Yu
patent: 7420201 (2008-09-01), Langdo et al.
patent: 11-026757 (1999-01-01), None
patent: 11-261063 (1999-09-01), None
patent: 2000-188394 (2000-07-01), None
Shu-Fen Hu, et al; “A Dual-Gate-Controlled Single-Electron Transistor Using Self-Aligned Polysilicon Sidewall Spacer Gates on Silicon-on-Insulator Nanowire”, IEEE Transactions on Nanotechnology, vol. 3, No. 1, Mar. 2004, pp. 93-97.
A Chatterjee, et al; “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”, Electron Devices Meeting, 1997, IEDM apos;97. Technical Digest., International Volume, Issue, Dec. 7-10, 1997, pp. 821-824.
International Search Report mailed Mar. 9, 2007, PCT/KR2006/005173.
Namatsu Hideo et al; “Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations”, Journal of Vacuum Science & Technology B: Microelectronicprocessing and Phenomena, American Vacuum Society, New York, NY, US, vol. 16, No. 1, Jan. 1, 1998, pp. 69-76, XP012006654, ISSN: 0734-211X, abstract.
Larrieu Guilhem et al; “Reactive ion etching of a 20 nanometers tungsten gate using a SF6/N2chemistry and hydrogen silsesquioxane hard mask resist”, Journal of Vacuum Science and Technology: Part B, AVS / AIP, Melville, New York, NY, US, vol. 23, No. 5, Sep. 16, 2005, pp. 2046-2050, XP01280124, ISSN: 1071-1023, abstract.
European Search Report: EP 06 82 3881.

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