Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1998-12-08

2001-08-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S234000, C438S700000

Reexamination Certificate

active

06271070

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device functioning as a Bi-CMOS including a high frequency bipolar transistor and a MOS transistor mounted on a common substrate.
Typical examples of transistors generally used at present include a bipolar transistor comprising an emitter, a base and a collector and a MOS transistor comprising a gate electrode, a gate oxide film and source/drain regions. A bipolar transistor is characterized by being suitably used in an analog device due to its linear amplifying function, and a MOS transistor is characterized by its simple structure and being suitably used in a logic element. Recently, a bipolar transistor is more widely used as a high frequency transistor, and there is a demand for a transistor suitable to a higher frequency. On the other hand, higher integration is required of a MOS transistor.
Furthermore, a semiconductor device using a high frequency bipolar transistor and a MOS transistor is recently required to be more compact. In order to attain compactness of such a semiconductor device, it is effective to build the semiconductor device in one chip with both the transistors mounted on a common substrate. Accordingly, the so-called Bi-CMOS device including a bipolar transistor and a MOS transistor mounted on a common substrate has been proposed.
Now, a conventionally proposed method of manufacturing a Bi-CMOS device will be described with reference to accompanying drawings.
FIGS. 16 through 24
are sectional views for showing conventional manufacturing procedures for the Bi-CMOS device.
First, in the procedure shown in
FIG. 16
, a main surface of a p-type silicon substrate
101
is oxidized, thereby forming a silicon oxide film thereon. The silicon oxide film is then etched by using a photoresist film (not shown) formed by the lithography on the silicon oxide film as a mask, so as to selectively remove the silicon oxide film. Thus, a mask oxide film
106
having an opening in a bipolar transistor forming region Rbp and an opening in a MOS transistor forming region Rmos is formed.
Next, by using the mask oxide film
106
as a mask, arsenic ions
107
are implanted into the main surface of the p-type silicon substrate
101
under conditions of, for example, at an acceleration energy of 30 keV and a dose of 1.5×10
15
cm. Thus, deep ion implanted layers
102
and
103
are formed respectively in the bipolar transistor forming region Rbp and the MOS transistor forming region Rmos.
Then, a heating treatment is conducted so that the arsenic in the deep ion implanted layers
102
and
103
can be diffused and the deep ion implanted layers
102
and
103
can be oxidized for forming a step for patterning. The mask oxide film
106
is then entirely removed.
Next, in the procedure shown in
FIG. 17
, an epitaxial layer
105
is grown on the entire main surface of the p-type silicon substrate
101
. At this point, the arsenic is partially diffused from the deep ion implanted layers
102
and
103
formed along the main surface of the p-type silicon substrate
101
into the epitaxial layer
105
, thereby forming n-type buried layers
108
and
109
.
Then, a silicon oxide film
110
and an active region forming silicon nitride film
111
are successively formed on the epitaxial layer
105
. Thereafter, openings are formed in the active region forming silicon nitride film
111
correspondingly to the bipolar transistor forming region Rbp and a PMOSFET forming region Rpmos in the MOS transistor forming region Rmos. Phosphorus ions
112
are implanted through these openings, thereby forming surface diffusion layers
113
in the bipolar transistor forming region Rbp and the PMOSFET forming region Rpmos.
Next, in the procedure shown in
FIG. 18
, the silicon oxide film
110
is removed, and a silicon region in each opening is selectively oxidized, thereby forming a mask oxide film
115
. Through the heat treatment for this oxidation, the impurity in the surface diffusion layer
113
is widely diffused, and hence, an n-type well region
114
is formed and the n-type buried layers
108
and
109
are enlarged in their depths.
Subsequently, in the procedure shown in
FIG. 19
, boron ions
116
are implanted into an NMOSFET forming region Rnmos in the MOS transistor forming region Rmos and the like by using the mask oxide film
115
as a mask, thereby forming a p-type implanted layer.
Then, in the procedure shown in
FIG. 20
, the mask oxide film
115
is removed and drive-in is conducted through a heat treatment, thereby forming a p-type well region
117
. Through this heat treatment, the N-type buried layers
108
and
109
are further enlarged in their depths.
Next, in the procedure shown in
FIG. 21
, after forming a LOCOS forming silicon nitride film
118
on the substrate, isolation oxide films
119
a
through
119
e
are formed in predetermined isolation regions by the general LOCOS method.
Then, in the procedure shown in
FIG. 22
, after growing a silicon oxide film
120
on the substrate, the isolation oxide films
119
a
and
119
c
including portions directly above the edges of the n-type buried layer
109
in the bipolar transistor forming region Rbp and substantially the center portions of the silicon oxide film
120
above the isolation oxide films
119
a
and
119
c
are selectively removed. Thus, trench openings
121
are formed.
Subsequently, in the procedure shown in
FIG. 23
, the silicon substrate exposed within each trench opening
121
is etched by using the silicon oxide film
120
as a mask, thereby forming a trench
122
with a depth of approximately 5 through 6 &mgr;m.
Furthermore, in the procedure shown in
FIG. 24
, after forming a channel stopper layer
123
below the bottom of each trench
122
, a sidewall oxide film
124
of the trench
122
is formed. Then, the trench
122
is buried with polysilicon, thereby forming a buried polysilicon layer
125
. The buried polysilicon layer
125
is formed by depositing a polysilicon layer on the substrate and etching back the polysilicon film through the dry etching.
The procedures thereafter are not described in detail, through which diffusion layers, electrodes and the like of a bipolar transistor, a PMOSFET and an NMOSFET are formed.
The Bi-CMOS device manufactured in the aforementioned manner can exhibit the following effects because it adopts a trench isolation structure instead of a LOCOS isolation structure: Due to the trench isolation structure, the junction capacitance between a collector in the bipolar transistor forming region Rbp and the substrate can be decreased, resulting in making the bipolar transistor applicable to a higher frequency. Also, since the trench isolation structure is adopted instead of the LOCOS isolation structure, the width of the isolation oxide films
119
a
through
119
e
can be decreased as compared with that of PN junction isolation. As a result, the line capacitance can be decreased and the device is applicable to a further higher frequency.
In forming the isolation, the trench is buried not with a silicon oxide film, which is used in a trench structure in a MOS transistor, but with polysilicon. This is for the following reasons: First, since it is necessary to conduct a heat treatment at a high temperature of approximately 900° C. after forming the trench isolation in manufacturing a bipolar transistor, occurrence of defects in the active region derived from a difference in the coefficient of thermal expansion between the silicon substrate and the material within the trench is thus avoided. Secondly, polysilicon in a small grain size having directivity is good in a burying characteristic such as coverage in a groove much deeper than a trench isolation of a MOS transistor, and hence, occurrence of voids unavoidable in using a silicon oxide film can be thus avoided. Accordingly, the trench is buried with polysilicon, and the sidewall oxide film
124
is formed between the buried polysilicon layer
125
and the p-type silicon substrate
101
.
Thereafter, although not shown

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