Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-24
2001-03-27
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S306000, C438S307000
Reexamination Certificate
active
06207518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to LD (Lateral Double Diffused) MOS transistor technology which is used for a high voltage element for e.g. liquid crystal driving IC.
2. Description of the Related Art
Now, an LDMOS transistor structure refers to a structure in which impurities with a different conduction type are diffused in a diffused region formed on surface of a semiconductor substrate to form another diffused region and a difference in the horizontal diffusion between these diffused regions is employed as an effective channel length. This structure, in which a short channel is formed, can constitute an element with low “on” resistance.
FIG. 10
is a sectional view for explaining a conventional LDMOS transistor which are being developed by the inventors of the invention. A N-channel LDMOS transistor structure is illustrated. Although the structure of a P-channel LDMOS transistor structure is not explained here, it is well known that the same structure can be adopted except for its conduction type.
In
FIG. 10A
, reference numeral
1
denotes a semiconductor substrate with a first conduction type, e.g. P-type, and reference numeral
21
denotes a P-type well region. A P-type body region
3
is formed within the P-type well region
21
. An N-type diffused region
4
is formed within the P-type body region
3
. Another N-type diffused region
5
is formed apart from the N-type diffused region
4
. A gate electrode
7
is formed on the surface of the substrate
1
through a gate insulating film
6
. A channel region
8
is formed in the surface region of the P-type body region
3
immediately below the gate electrode.
The N-type diffused region
4
is used as a source region whereas the N-type diffused region is used as a drain region. A drift region (N
−
layer
22
) is formed which is composed of a shallow region (first N
−
layer
22
A) below the gate electrode
7
and deep region (second N
−
layer
22
B) in the vicinity of the drain region. Further, a source electrode and drain electrode (not shown) are formed on the surface so as to contact with source and drain region, respectively. A P-type diffused region
12
for assuming the potential of the P-type body region
3
is formed through an interlayer insulating film.
In the above LDMOS transistor, which has a high impurity concentration on the surface of the N-type drift region, a current is apt to flow in the surface of the N-type drift region, thereby realizing a high withstand voltage. The LDMOS transistor having such a configuration is referred to as a surface relax type (RESURF)LDMOS.
However, since the impurity concentration is high in the surface of the N-type drift region
22
, the P-type body region
3
cannot diffuse sufficiently. Therefore, as shown in
FIG. 10B
, the edge of the P-type body region
3
approaches the source region (N-type diffused region
4
) so that the channel region B may be not be formed to have a suitable size and impurity concentration(see indicated arrow).
The inventors of the invention tried to solve the above problem by rearranging the manufacturing steps and eventually completed the present invention. Specifically, in the conventional process, the drift region (N
−
layer
22
) was formed in such a manner that at least two N-type impurities (phosphorus ions or arsenic ions) with different diffusion coefficients are ion-implanted and diffused in the surface layer of the P-type well region
21
, and thereafter P-type impurities (boron ions) are ion-implanted and diffused into the surface layer of the P-type well region
21
where the source region is to be formed so that the boron ions thus diffused cancel the phosphorous ions of the second N
−
layer
22
B (diffused layer originating from phosphorus ions) formed at a relatively deep position of the P-type well region of the source region.
However, the following fact was confirmed. The drift region (N
−
layer
22
), after it has been formed, is subjected to thermal oxidation to form a gate insulating film
6
. Therefore, arsenic ions contained in the first N
−
layer (with arsenicions diffused) are segregated on the substrate surface. Because of the segregated arsenic ions, the P-type body region does not diffuse sufficiently so that the channel region
8
cannot be formed to have a suitable size (see a hatched region showing segregated ions in the graph of FIG.
9
).
SUMMARY OF THE INVENTION
An object of the invention is to provide a method of manufacturing a semiconductor device which can satisfy the requirements of a high withstand voltage and reduced “on” resistance.
Namely the present invention intends to reduce a defect of channel caused by the segregation of the impurity ion for forming a drift region in a semiconductor device having the drift region near the channel region, thereby a reliable LDMOS type transistor can be obtained.
In order to achieve the above object, in accordance with the invention, there is provided a method of manufacturing a semiconductor device which includes a source region
4
, a channel region
8
and a drain region
5
, a gate electrode
7
formed on the channel region through a gate insulating film
6
and a drift region (N
−
layer
22
) formed between the channel region and the drain region, wherein the process of forming the drift region (N
−
layer) comprises the steps of: ion-implanting and diffusing at least two kinds of second conduction type impurities (e.g. phosphorus and arsenic ions) having different diffusion coefficients in a P-type well region
21
; ion-implanting at least one kind first conduction type impurities (e.g. boron ions) having a diffusion coefficient substantially equal to or larger than that of at least one of said second conduction type impurities (e.g. phosphorus); and diffusing the first conduction type impurities after the gate insulating film
6
has been formed.
Preferably, the step of diffusing the first conduction type impurities is executed after a film for forming said gate electrode (polysilicon film
17
) has been formed.
In accordance with the invention, since the first conduction type impurities for forming a drift region with the first conduction type are diffused after the thermal oxidation for forming the gate insulating film, it is possible to solve the problem that the body region with the first conduction type does not diffuse sufficiently owing to a drift region with the second conduction type, thereby permitting a suitable channel region to be formed and providing a semiconductor device which can satisfy the requirement of high withstand voltage and reduced “on” resistance.
In addition, where the step of diffusing the first conduction type impurities for forming the drift region with the first conduction type is executed before the film for forming a gate electrode is made conductive, it is possible to solve the problem that the temperature of the viscous flow of the gate insulting film is made lower than that of the normal viscous flow by the impurities used to make conductive the film for forming the gate electrode, and hence while the first conduction type impurities are diffused, the gate insulating film of SiO
2
film is exposed to an atmosphere of the higher temperature than the temperature when the viscous flow occurs, thereby avoiding the occurrence of the phenomenon of reducing the withstand voltage of the oxide film.
The above and other objects and features of the invention will be more apparent from the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5541123 (1996-07-01), Williams et al.
patent: 537684 (1993-04-01), None
patent: 802567 (1997-10-01), None
patent: WO8403997 (1984-10-01), None
Akaishi Yumiko
Kikuchi Shuichi
Dang Trung
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
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