Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Utility Patent
1999-10-19
2001-01-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S623000, C438S624000
Utility Patent
active
06169040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique for forming a dielectric film on an underlying layer having an uneven surface.
2. Description of the Related Art
Several techniques have been proposed for flattening the upper surface of an inter-metal dielectric film when a semiconductor device such as VLSI (very large scaled integration) is manufactured. FIGS.
9
-
13
show an example of a process for manufacturing a semiconductor device using a conventional technique for flattening an inter-metal dielectric film.
According to the conventional manufacturing process, as shown in
FIG. 9
, a semiconductor substrate
1
on which a field oxide film
2
is formed is prepared. On the field oxide film
2
and semiconductor substrate
1
, a MOSFET (metal-oxide-silicon field effect transistor)
7
including a polycrystalline silicon gate
5
is formed.
A pre-metal dielectric film (PMD)
3
is formed so as to cover these regions. The pre-metal dielectric film
3
is made of e.g. PSG (phosphorus-doped silicon oxide film) or BPSG (boron-and-phosphorus doped silicon oxide film). An aluminum wiring
4
is formed on the pre-metal dielectric film
3
.
Using e.g. CVD (chemical vapor deposition) technique, a USG (undoped silicate glass) is deposited to form an USG layer
6
. Using SOG (Spin On Glass) technique, an organic SOG layer is formed thereon by application in such a manner that it is embedded in the upper concave areas or grooves of the USG layer. The organic SOG layer is made of a dielectric material whose thick layer can be easily formed.
As shown in
FIG. 10
, an unnecessary area of the organic SOG layer is removed by etch back. The etch back step is executed in a manner of slight over-etch so that the organic SOG layer
8
is not left immediately above the aluminum wiring layer
4
. Thus, as seen from
FIG. 10
, the upper surface of the organic SOG layer
8
which is left on the upper surface of the USG layer
6
is also slightly lowered.
In order that the lowered area is embedded, as shown in
FIG. 11
, an inorganic SOG layer
10
of an inorganic dielectric material with a high pattern-following property is formed by application. Further, as shown in
FIG. 12
, an unnecessary area of the inorganic SOG layer
10
is removed by etch-back. Thus, the concave area in the upper surface of the USG layer
6
is substantially completely embedded with the inorganic SOG layer
10
.
Further, using CVD technique, USG is deposited thereon to form a USG layer
12
. In this way, an inter-metal dielectric layer
14
is formed.
In this way, the concave area or groove on the upper surface of the USG layer
6
is embedded with the organic SOG layer
8
made of an organic dielectric material which can easily provide its thick layer and the inorganic SOG layer
10
made of an inorganic dielectric material with a high pattern-following property. In addition, the SOG layers
8
and
10
having relatively poor substance quality (not fine) are encircled by the USG layers
6
and
12
having a fine and relatively good substance quality. Thus, an inter metal insulating film
14
having an flat upper surface with excellent insulating property can be obtained.
However, the above conventional method of forming an inter metal dielectric film
14
has the following defects. The SOG process requires a number of steps and activities. For example, after the SOG layer has been applied and before the unnecessary area is removed by etch back, the steps of measuring the thickness of the applied SOG layer and annealing it are required. The etch back process for the SOG layer requires a step of measuring the thickness of the remaining film. After the etch back process, in order to remove the particles generated in the etch back process, a desquamation step using O
2
plasma and a scrubber step using a brush are required. In addition, silicon compound (in generally such as R
n
Si(OH)
4−n
) used as the dielectric material in the SOG process is relatively expensive.
The above conventional method of forming an inter-metal dielectric film
14
in which the SOG step must be made twice have defects of requiring a long lead time and high production cost. The present invention intends to overcome these defects.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device which can form a dielectric film with an upper flat surface with an excellent dielectric property at low cost and in a short lead time.
In order to attain the above object, in accordance with the present invention, there is provided a method of manufacturing a semiconductor device having an inter-metal dielectric film composed of a first dielectric film and a second dielectric film formed by a process comprising the steps: depositing the first dielectric film silicon oxide on an underlying wiring layer having an uneven surface; applying organic SOG on the first dielectric film thus formed, and etching back the organic SOG thus applied so that the organic SOG remains in a groove in a surface of the first dielectric film; and depositing the second dielectric film on said first dielectric film inclusive of the remaining organic SOG through a vapor phase growth method using high density plasma.
Thus, the organic SOG layer whose thick layer can be easily formed is left so that the unevenness of the surface of the USG layer is relaxed in a degree. In addition, the USG layer is formed through the vapor phase growth technique using the high density plasma which can realize excellent embedding. Accordingly, the inter-metal dielectric film having a flat upper surface can be formed.
The SOG step accompanied by high cost is carried out only once in the step of forming the organic SOG layer. The step of forming the inorganic SOG layer is not required so that the production cost can be reduced correspondingly. The lead time required for production can be also shortened. As a result, the cost required for forming the inter-metal dielectric film can be reduced and the lead time for production can be shortened.
Further, since the organic SOG layer left in the groove on the surface of the USG layer can be encircled by the USG layers and having good film quality, even if the material of the organic SOG layer is not so good, the inter-metal dielectric film with excellent dielectric property can be formed.
In summary, the inter-metal dielectric film having a flat upper surface with excellent dielectric property can be formed at low cost and in a short lead time.
A second aspect of the method is a method according to the first aspect, wherein the step of forming the first dielectric film comprises a step of forming a silicon oxide film through CVD.
A third aspect of the method is a method according to the first aspect, wherein the step of forming the second dielectric film comprises a step of forming a silicon oxide film through a vapor phase growth technique using the high density plasma.
A fourth aspect of the method is a method according to the first aspect, wherein the step of applying organic SOG comprises the step of etching back the organic SOG thus applied so that the organic SOG remains in a groove whose opening diameter is more than 0.1 &mgr;m; and
the step of forming the second dielectric film comprises a step of forming a silicon oxide film through a vapor phase growth technique using the high density plasma so that the groove is embedded.
A fifth aspect of the method is a method of manufacturing a semiconductor device having a dielectric film composed of a first dielectric film and a second dielectric film formed by a process comprising the steps:
depositing silicon oxide on an underlying wiring layer having an uneven surface to form the first dielectric film;
filling a groove of the first dielectric film thus formed with a dielectric material; and
forming the second dielectric film on the first dielectric film inclusive of the filled dielectric through a vapor phase growth method us
Kageyama Satoshi
Mifuji Michihiko
Ghyka Alexander G.
Morgan & Lewis & Bockius, LLP
Niebling John F.
Rohm & Co., Ltd.
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