Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-28
2003-09-16
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S264000, C438S266000, C257S315000, C257S320000
Reexamination Certificate
active
06620684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a nonvolatile memory cell, and more particularly to, a method of manufacturing a nonvolatile memory cell capable of enhancing a retention characteristic of the nonvolatile memory using selective oxidation.
2. Description of the Prior Art
Semiconductor memory device can be classified into RAM (random access memory) products such as DRAM (dynamic random access memory) and SRAM (static random access memory), and ROM (read only memory). RAM is volatile since the data in RAM is lost in time but ROM is nonvolatile since the data in ROM is not lost. Also, the input/output speed of data in RAM is fast but the input/output speed of data in ROM is low. This ROM product family may include ROM, PROM (programmable ROM), EPROM (erasable programmable ROM) and EEPROM (electrically erasable programmable read-only memory). Among them, a demand for EEPROM from which data is electrically programmable and erasable has been increased. The EEPROM or a flash EEPROM has a stack type gate structure in which a floating gate electrode and a control gate electrode are stacked.
The memory cell of the stack type gate structure programs/erases data by means of Fowler-Nordheim (F-N) tunneling and has a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode stacked on a semiconductor substrate. The gate electrodes have a stack structure in which a polysilicon layer into which an impurity having a strong heat-resistance is doped or a polysilicon layer and a tungsten silicide (WSix) are stacked.
Generally, after the gate electrodes are formed, a high temperature annealing process for compensating for etching damage generated when a pattern of the gate electrode is formed is performed. At this time, however, there occurs a GGO (graded gate oxide) phenomenon in which a silicon substrate at an edge portion of the tunnel oxide film is oxidized/grown due to the annealing process. The GGO phenomenon is generated between the floating gate electrode and the semiconductor substrate to keep them by a given distance, thus solving a retention problem that is most important in the nonvolatile memory.
There was proposed “In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WNx on polycrystalline Si, LG, SEMICONDUCTOR CO. LTD., issued by Byung-Hak Lee etc. (IEEE, 1998). This paper proposes a resistance variation ratio to the width of the gate electrode formed of tungsten silicide (WSix) or tungsten (W).
Seeing a characteristic graph relating to the resistance variation ratio to the width of the gate electrode shown in this paper, if the width of the gate electrode is reduced to below 0.2 &mgr;m, the resistance of the gate electrode formed of tungsten silicide (WSix) is abruptly increased while the resistance of the gate electrode formed of tungsten (W) is almost constant with no regard to reduced width. In other words, as the wired of the gate electrode formed of tungsten silicide (WSix) is reduced to below 0.2 &mgr;m, the resistance is abruptly increased while the resistance of the gate electrode formed of tungsten (W) is almost constant with no regard to reduced width.
Therefore, when the gate electrode is formed of tungsten silicide (WSix), there is a problem that a RC delay time is delayed since the resistance is increased as the memory cell is higher integrated. Due to this, there is a need for a method for forming a gate electrode using tungsten (W) in order to implement higher integrated memory cell.
However, tungsten (W) is abnormally oxidized since it easily reacts with oxygen at a high temperature. Therefore, there occurs a problem that an upper surface characteristic of the gate electrode is degraded since tungsten (W) is abnormally oxidized at a high temperature annealing process. Recently, in order to solve this problem, there has been proposed a selective oxidation process instead of the high temperature annealing process. Though the selective oxidation process can prevent abnormal oxidization of tungsten (W), it does not sufficiently oxidize the upper surface of the semiconductor substrate at an edge portion of the tunnel oxide film. Thus, there is a problem that it does not solve a retention problem of the nonvolatile memory cell.
Therefore, there is a need for a method capable of solving a retention problem in a nonvolatile memory cell when a gate electrode is formed using tungsten (W).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a nonvolatile memory cell capable of solving a high temperature annealing problem occurring when a gate electrode is used, in a way that the gate electrode is formed using tungsten (W) in order to implement integration of the nonvolatile memory cell.
In order to accomplish the above object, a method of manufacturing a nonvolatile memory cell according to the present invention, is characterized in that it comprises the steps of forming a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode on a semiconductor substrate; forming source and drain region by means of source/drain ion implantation process; forming an oxide layer on the source and drain region by means of selective oxidization process; and forming spacers on both sides of the floating gate electrode and the control gate electrode.
Also, a method of manufacturing a nonvolatile memory cell according to the present invention, is characterized in that it comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon layer, a dielectric film, a second polysilicon layer, a tungsten layer and a hard mask layer a semiconductor substrate; etching the hard mask layer, the tungsten layer, the second polysilicon layer and the dielectric film in one direction to form a control gate electrode; performing a first selective oxidization process to form a first oxide layer on both sides of the second polysilicon layer and the dielectric film; forming a first spacer on both sides of the control gate electrode; etching the first polysilicon layer and the tunnel oxide film to form a floating gate electrode; performing source/drain ion implantation process to form a source and drain region; performing a selective oxidization process to form a second oxide film on the source and drain region; and forming a second spacer on both sides of the floating gate electrode and the control gate electrode.
REFERENCES:
patent: 6143609 (2000-11-01), Sato et al.
patent: 6288419 (2001-09-01), Prall et al.
Byung Hak Lee et al., “In-situ Barrier Formation for High Reliable W/barrier/poly-Si Gate Using Denudation of WNxon Polycrystalline Si”. 1998 IEEE.
Cho Min Kuck
Jung Sung Mun
Kim Jum Soo
Lee Sang Bum
Lee Young Bok
Chen Jack
Hynix / Semiconductor Inc.
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