Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-29
2004-08-24
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S593000, C257S314000, C257S315000, C257S316000
Reexamination Certificate
active
06780710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile ROM (Read Only Memory) such as mask ROM and More specifically, the present invention relates to non-volatile ROM which can store quaternary data.
2. Description of Related Art
Mask ROM is an example of known non-volatile Read Only Memory. Mask ROM that is able to write quaternary data into each memory cell transistor has been known for some time. A large amount of information can be stored in small circuits using this mask ROM. Examples of known mask ROM that can store quaternary data include the mask ROM disclosed in Japanese Laid-open Publication No. 1996-316341 (hereinafter referred to as Document 1) and the mask ROM disclosed in Japanese Laid-open Publication No. 1996-288408 (hereinafter referred to as Document 2).
The mask ROM of Document 1 achieves storing the quaternary data by using the fact that the threshold value of a cell transistor changes when a lightly doped drain (LDD) area is provided in the diffusion area. In other words, the threshold value of transistor changes depending on the type of structure adopted: a structure in which an LDD area is provided in both the source area and drain area; a structure in which an LDD area is provided only in the source area; a structure in which an LDD area is provided only in the drain area; or a structure in which an LDD area is provided in neither the source area or drain area. The differences in the threshold value are determined by comparing the current between source and drain when the prescribed gate voltage is applied to each transistor.
The mask ROM of Document 2 achieves storing the quaternary data by using the fact that when a p+ diffusion area is provided next to an n-type source area the cell transistors are non-conductive whereas when a p+ diffusion area is provided next to an n-type drain area the cell transistors are conductive. In other words, when a p+ diffusion area is placed next to only one of two n-type diffusion areas in a cell transistors the cell transistor is conductive when this n-type diffusion area is used as the source, but the cell transistor is not conductive when the other n-type diffusion area is used as the source. Also, when p+ diffusion areas are provided in both n-type diffusion areas in a cell transistor, the cell transistor is not conductive regardless of which n-type diffusion area is used as the source. Furthermore, in cell transistors without any p+ diffusion area, the cell transistor is conductive no matter which n-type diffusion area is used as the source. Accordingly, storing quaternary data is achieved by adopting either of the following structures: a structure in which both of n-type diffusion areas are provided with a p+ diffusion area; a structure in which only one n-type diffusion area is provided with a p+ diffusion area; a structure in which the other n-type diffusion area is provided with a p+ diffusion area; or a structure in which no n-type diffusion area is provided with a p+ diffusion area. Quaternary data can then be read using combinations of the distinction of conductive and non-conductive of a cell transistor when one diffusion area is used as the source and the distinction of conductive and non-conductive of the cell transistor when the other diffusion area is used as the source.
Also, the mask ROM of Document 2 uses n-type source areas and n-type drain areas as wiring, and forms word lines as gate electrodes by making them cross over these n-type source areas and n-type drain areas.
However, the mask ROMs according to Documents 1 and 2 have the following disadvantages.
One of the disadvantages of the mask ROM of Document 1 is the lengthy Turn Around Time (TAT). TAT is the time required from presentation of a program with writing data by the user to its delivery by mask ROM. To reduce TAT, it is preferable that as few processes as possible come after data is written, that is, it is preferable to ensure that as many processes as possible are common processes that can be implemented before data is written. However, in the mask ROM of Document 1, the LDD creation process, which is the data writing process, must be implemented prior to the creation of the source diffusion area and drain diffusion area. Therefore, the source and drain diffusion areas cannot be created in a common process and accordingly there is a lengthy TAT.
Furthermore, because there is only a small difference in the threshold values based on the LDD area, the read data in the mask ROM in Document 1 is not adequately reliable.
On the other hand, the disadvantage of the mask ROM of Document 2 is that the p+ diffusion layer is difficult to create. In other words, in this mask ROM, data is written (that is, the p+ diffusion area is created) after word lines are formed and so the p+ diffusion area with high reliability cannot be formed. Also, in this mask ROM, a diffusion area with a conductivity that is the opposite of the conductivity of the source and drain areas (that is p conductivity) must be formed in an extremely small area, however, it is difficult to form photo resistors for implantation of impurities in a small area and therefore, it is difficult to refine cell sizes and very accurately control cell currents.
Furthermore, the mask ROM in Document 2 uses n-type source areas and n-type drain areas as wiring and so line resistance is high. This has the disadvantage of inhibiting fast and stable reading of data.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile Read Only Memory with a short TAT, in which cells can be easily refined and data can be read with stability.
To enable this, the non-volatile Read Only Memory according to the present invention comprises: memory cell transistors each of which is constituted such that the area between the gate electrode and one impurity area and the area between the gate electrode and the other impurity area take offset structure or non-offset structure in accordance with the value of stored data; a row selection line that applies a voltage to the gate electrodes in the memory cell transistors belonging to same row; a first column selection line that applies a voltage to the one impurity area in the memory cell transistors belonging to same column; a second column selection line that applies a voltage to the other impurity area in the memory cell transistors belonging to same column; and reading means which applies a read electric potential to the row selection line selected, and reads the stored data by detecting the on/off status of the memory cell transistors when high electric potential is applied to the first column selection line and low electric potential is applied to the second column selection line, and by detecting the on/off status of the memory cell transistors when low electric potential is applied to the first column selection line and high electric potential is applied to the second column selection line.
The memory relating to the present invention writes data using the offset or non-offset structure of the memory cell transistors. The data is then read according to the combination of the on/off status of memory cell transistors when a high electric potential is applied to the first column selection line and a low electric potential is applied to the second column selection line and the on/off status of memory cell transistors when a low electric potential is applied to the first column selection line and a high electric potential is applied to the second column selection line.
In the present invention, an “offset structure” describes a structure in which an ON-current flows in a transistor when the impurity area is used as a drain in that transistor but in which an ON-current does not flow when the impurity area is used as a source. Also, in the present invention, a “non-offset structure” describes a structure in which an ON-current flows in a transistor when the impurity area is used either as a drain or as a source in that transistor.
A firs
Egawa Noboru
Kokubun Hitoshi
Le Dung A.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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