Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-09-21
2009-10-20
Pham, Thanhha (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S216000, C438S593000, C438S594000
Reexamination Certificate
active
07605067
ABSTRACT:
A method of manufacturing a non-volatile memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.
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patent: 6803272 (2004-10-01), Halliyal et al.
patent: 1020050045737 (2005-05-01), None
patent: 1020050121174 (2005-12-01), None
patent: 1020060024189 (2006-03-01), None
English Abstract for Publication No. 1020060024189.
English Abstract for Publication No. 1020050121174.
English Abstract for Publication No. 1020050045737.
Choi Han-Mei
Kim Sun-Jung
Lee Seung-Hwan
Park Ki-Yeon
Ryu Min-Kyung
F. Chau & Associates LLC
Pham Thanhha
Samsung Electronics Co,. Ltd.
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