Method of manufacturing non-volatile memory device

Details Method of manufacturing non-volatile memory device Method of manufacturing non-volatile memory device

2003-05-28

2004-10-19

Zamela, David A. (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000

Reexamination Certificate

active

06806148

ABSTRACT:

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK.
Not Applicable
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and static random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.
Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of memories, including non-volatile and volatile memories. The volatile memory, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its stored data if the power applied has been turned off SRAMs and DRAMs often include a multitude of memory cells disposed in a two dimensional array. Due to its larger memory cell size, an SRAM is typically more expensive to manufacture than a DRAM. An SRAM typically, however, has a smaller read access time and a lower power consumption than a DRAM. Therefore, where fast access to data or low power is needed, SRAMs arc often used to store the data.
Non-volatile semiconductor memory devices are also well known. A non-volatile semiconductor memory device, such as flash Erasable Programmable Read Only Memory (Flash EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) or, Metal Nitride Oxide Semiconductor (MNOS), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data
Unfortunately, the non-volatile semiconductor memory is typically slower to operate than a volatile memory. Therefore, where fast store and retrieval of data is required, the non-volatile memory is not typically used. Furthermore, the non-volatile memory often requires a high voltage, e.g., 12 volts, to program or erase. Such high voltages may cause a number of disadvantages. The high voltage increases the power consumption and thus shortens the lifetime of the battery powering the memory. The high voltage may degrade the ability of the memory to retain its charges due to hot-electron injection. The high voltage may cause the memory cells to be over-erased during erase cycles. Cell over-erase results in faulty readout of data stored in the memory cells.
The growth in demand for battery-operated portable electronic devices, such as cellular phones or personal organizers, has brought to the fore the need to dispose both volatile as well as non-volatile memories within the same portable device. When disposed in the same electronic device, the volatile memory is typically loaded with data during a configuration cycle. The volatile memory thus provides fast access to the stored data. To prevent loss of data in the event of a power failure, data stored in the volatile memory is often also loaded into the non-volatile memory either during the configuration cycle, or while the power failure is in progress. After power is restored, data stored in the non-volatile memory is read and stored in the volatile memory for future access. Unfortunately, most of the portable electronic devices may still require at least two devices, including the non-volatile and volatile, to carry out backup operations. Two devices are often required since each of the devices often rely on different process technologies, which are often incompatible with each other.
To increase the battery life and reduce the cost associated with disposing both non-volatile and volatile memory devices in the same electronic device, non-volatile SRAMs and non-volatile DRAMs have been developed. Such devices have the non-volatile characteristics of non-volatile memories, i.e., retain their charge during a power-off cycle, but provide the relatively fast access times of the volatile memories. As merely an example,
FIG. 1
is a transistor schematic diagram of a prior art non-volatile DRAM
10
. Non-volatile DRAM
10
includes transistors
12
,
14
,
16
and EEPROM cell
18
. The control gate and the drain of EEPROM cell
18
form the DRAM capacitor. Transistors
12
and
14
are the DRAM transistors. Transistor
16
is the mode selection transistor and thus selects between the EEPROM and the DRAM mode.
FIG. 2
is a transistor schematic diagram of a prior art non-volatile SRAM
40
. Non-volatile SRAM
40
includes transistors
42
,
44
,
46
,
48
,
50
,
52
,
54
,
56
, resistors
58
,
60
and EEPROM memory cells
62
,
64
. Transistors
48
,
50
,
52
,
54
and resistors
58
,
60
form a static RAM cell. Transistors
42
,
44
,
46
,
56
are select transistors coupling EEPROM memory cells
62
and
64
to the supply voltage Vcc and the static RAM cell. Transistors
48
and
54
couple the SRAM memory cell to the true and complement bitlines BL and {overscore (BL)}.
EEPROM
18
of non-volatile DRAM cell
10
(
FIG. 1
) and EEPROM
62
,
64
of non-volatile SRAM cell
40
(
FIG. 2
) may consume require a high programming voltage and thus may suffer from high-voltage related stress. Accordingly, a need continues to exist for a relatively small non-volatile memory device that, among other things, is adapted for use in a non-volatile SRAM or DRAM and consume less power than those known in the prior art.
While the invention is described in conjunction with the preferred embodiments, this description is not intended in any way as a limitation to the scope of the invention. Modifications, changes, and variations, which are apparent to those skilled in the art can be made in the arrangement, operation and details of construction of the invention disclosed herein without departing from the spirit and scope of the invention.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a method of forming an integrated circuit in a semiconductor substrate, includes, in part, the steps of: forming at least two trench isolation regions in the semiconductor substrate, forming a first well between the two trench isolation regions, forming a second well between the two trench isolation regions and above the first well to define a body region, forming a first oxide layer above a first portion of the body region, forming a first dielectric layer above the first oxide layer, forming a first polysilicon layer—that forms a control gate of a non-volatile device—above the first dielectric layer, forming a second dielectric layer above the first polysilicon layer, forming a first spacer above the body region and adjacent said first polysilicon layer, forming a second oxide layer above a second portion of the body region that is not covered by the first spacer, forming a second polysilicon layer—that forms a guiding gate of the non-volatile device—above the second oxide layer, the first spacer and a portion of the second dielectric layer, forming a second spacer above the body region to define source and drain regions of the non-volatile device, and delivering n-type implants in the defined source and drain regions of the non-volatile device.
In some embodiments, the semiconductor substrate is a p-type substrate. In such embodiments, the first well is an n-well formed using a number of implant steps each using a different energy and doping concentration of phosphorous. Furthermore, in such embodiments, the second well is a p-well formed using a number of implant steps each using a different energy and doping concentration of boron. In some embodiments, the implant steps used to form the n-well and p-well are carried out using a single masking step.
In some embodiments, the first dielectric layer further includes an oxide layer and a nitride layer and the second dielectric lay

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