Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-06-13
2006-06-13
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S263000
Reexamination Certificate
active
07060560
ABSTRACT:
A method of manufacturing a non-volatile memory cell includes forming a first dielectric layer on a substrate. A second dielectric layer having a trench is formed on the first dielectric layer. Thereafter, a pair of charge storage spacers is formed on sidewalls of the trench. A third dielectric layer is then formed over the substrate to cover the first dielectric layer, the charge storage spacers and second dielectric layer. A conductive structure is formed on the third dielectric layer over the charge storage spacers. Subsequently, portions of the third dielectric layer, the second dielectric layer and first dielectric layer not covered by the conductive structure are removed. Ultimately, source/drain regions are formed in the substrate at each side of the conductive structure.
REFERENCES:
patent: 6249022 (2001-06-01), Lin et al.
patent: 6635533 (2003-10-01), Chang et al.
patent: 2004/0207007 (2004-10-01), Lin et al.
Sung Da
Wu Sheng
Jiang Chyun IP Office
Powerchip Semiconductor Corp.
Tsai H. Jey
LandOfFree
Method of manufacturing non-volatile memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing non-volatile memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing non-volatile memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3670925