Method of manufacturing nano transistors

Details Method of manufacturing nano transistors Method of manufacturing nano transistors

2002-06-27

2004-09-28

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S705000, C438S706000, C438S715000

Reexamination Certificate

active

06797629

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a nano transistor using a SOI (silicon on insulator) substrate, and more particularly to, a method of manufacturing a nano transistor capable of controlling the threshold voltage and preventing increase of the leakage current, in such a way that a nanometers transistor formed is formed on the SOI substrate by a conventional method, and N-well and P-well are formed at given regions of an underlying silicon substrate so that a given voltage of the substrate can be individually applied to a NMOS transistor and a PMOS transistor.
2. Description of the Prior Art
As the length of a gate in a transistor is reduced to several run, there is a limit to controlling of the threshold voltage of the devices. In the case of silicon widely used as, for example, a semiconductor substrate, the lattice constant of silicon is about 5.4 Å (1 Å=10
−10
m). 5.4 Å corresponds 0.54 nm. In other words, if a gate having the length of 50 nm is used, the number of silicon atoms existing at a channel region formed below the gate is about 100. At this time, as the concentration of an impurity injected transistor is usually below 10
18
cm
−3
in order to control the threshold voltage of the, the impurity atoms less than 10 are distributed at the channel region of the transistor in case that boron, arsenic or phosphorus is injected.
Therefore, the impurity for controlling the threshold voltage of the transistor is distributed depending on its location. Fine variations in the concentration of the impurity generating at the channel region greatly affects the threshold voltage. Due to this, it is actually impossible to employ an impurity in order to control the threshold voltage in the transistor of about nanometers.
Meanwhile, there are other problems in case that the threshold voltage is difficult to control by implanting an impurity into the channel region. In order to manufacture a transistor having a nanometers size, it is required that the depth of a junction in source and drain regions be also formed to be very shallow. It was reported in recent researches that the junction depth of the source and drain is about 0.25 times than the gate length of the transistor. Therefore, the appropriate junction depth is about 12 nm, in case that the gate length is 50 nm. As well know in the art, however, the junction depth is likely to be very deep due to a low impurity concentration at the channel region, which increase the short channel effect of the transistor to degrade an electrical characteristic of the transistor. In order to solve this problem, a transistor having a nano meter size is fabricated on a silicon substrate of a SOI structure not a bulk structure. It was found that the short channel effect of the transistor can be reduced by making the thickness of the SOI substrate existing on a buried oxide (hereinafter called “BOX”) very shallow, so that the junction of the source and drain regions are formed to be shallow, as shown in FIG.
1
. As a method of controlling the threshold voltage at the channel region of the transistor using an impurity could not be applied to the above method, it is impossible to control an adequate threshold voltage and the characteristic of the leakage current is thus very degraded.
FIG. 1
is a cross-sectional view of a nano transistor for describing a method of manufacturing the nano transistor using a conventional SOI substrate.
As shown in
FIG. 1
, a silicon substrate
11
, a BOX layer
12
and a silicon layer are sequentially stacked on a substrate. The silicon layer is then removed except for regions where a gate electrode, source and drain in a NMOS transistor region A and a PMOS transistor region B will be formed. In the above, as the BOX layer
12
is formed to have the thickness of about 100~300 nm, the silicon substrate
11
and the silicon layer arc electrically completely separated. A gate insulating film
13
and a conductive layer are sequentially formed on remaining silicon layer and are then patterned to form a gate electrode
14
of the NMOS transistor A and a gate electrode
15
of the PMOS transistor B, respectively. A source and drain electrode
16
of the NMOS transistor A and a source and drain electrode
17
of the PMOS transistor B remaining on the silicon layer are each formed by a given impurity ion implantation process. As the silicon substrate
11
and the silicon layer are electrically completely separated by the BOX layer
12
in the nano transistor manufactured as above, the channel region of the transistor becomes a floating state to which no voltage is not applied. Therefore, a kink effect cause generated unwanted operation. In addition, as the thickness of the BOX layer is thick, no voltage is applied to the silicon substrate
11
.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the problems and an object of the present invention is therefore to provide a method of manufacturing a nano transistor capable of arbitrarily controlling the threshold voltage of a NMOS transistor and a PMOS transistor, in such as way that a voltage is applied to a SOI substrate not a conventional implantation of the impurity as it is impossible to control the threshold voltage by implanting the impurity into the channel region since the gate length of the transistor becomes below 50 nm.
In the present invention, as it is impossible to control the threshold voltage by controlling the concentration of an impurity in case that a device having a nanometers size is manufactured using a SOI substrate, a body effect is implemented using a silicon substrate existing below a BOX layer. Therefore, the threshold voltage of a NMOS transistor and a PMOS transistor can be adequately controlled as necessary.
In case that the SOI layer is completely depleted since the thickness of the SOI substrate is very thin, the threshold voltage of the transistor can be represented as follow using the depletion approximation.
V
th
=V
th0
−
(
V
bb
−V
ba
)  [Equation 1]
V
th0
=V
fb
+(1
+C
si
/C
ox
)2&phgr;
F
−0.5×
q
N
S
/
Cox
  [Equation 2]
where, V
th
is the threshold voltage of a transistor formed on a SOI layer that is completely depleted, V
bb
is a voltage applied to a silicon substrate, V
ba
is a characteristic constant value determined by manufacturing characteristics of a device, V
fb
is a planarization voltage, &phgr;
F
is the Fermi energy level, N
S
is the impurity concentration of a channel region, C
Si
is the capacitance of the SOI layer, C
OX
is the capacitance of the gate insulating film and q is the charge amount of electrons. Also,
indicates a value defined as a body factor and can be represented as the following equation, which represents variations against the voltage applied to the silicon substrate of the threshold voltage
=
dV
th
/dV
bb
  [Equation 3]
The body factor can be finally represented as below [Equation ] by means of approximation of
.
=the thickness of the gate insulating film/the thickness of the BOX layer  [Equation 4]
As can be seen from [Equation 4], therefore, the threshold of the voltage transistor formed on the SOI substrate can be controlled by a voltage applied to the substrate, by adequately controlling the thickness of the BOX layer. In the SOI substrate employed usually, the thickness of the gate insulating film is about 3 nm and the thickness of the BOX layer is about 100~300 nm, in a nanometers region. In this case, as the body factor approaches to nearly 0, the voltage of the substrate rarely affects the threshold voltage. If the thickness of the BOX layer is controlled to have about 30 nm, however, the value of the body factor is almost about 0.1. Also, if the substrate is applied with a voltage of about 1V, an actual threshold voltage is increased by about 0.1V or reduced. Therefore, if a desired threshold vol

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