Method of manufacturing multiple metallic layered embedded ROM

Details Method of manufacturing multiple metallic layered embedded ROM Method of manufacturing multiple metallic layered embedded ROM

1999-09-03

2000-11-14

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438278, H01L 218246

Patent

active

061469505

ABSTRACT:
A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region. The via hole exposes the first patterned metallic layer. A metallic barrier layer is formed over the substrate. Ions are implanted into coded regions in the substrate. A second patterned metallic layer is formed in the peripheral circuit region to cover the second dielectric layer and fill the via hole. A third patterned metallic layer is formed in the memory cell region to fill the contact opening. A passivation layer is formed over the substrate.

REFERENCES:
patent: 5681772 (1997-10-01), Chen et al.
patent: 5744394 (1998-04-01), Iguchi et al.

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